Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
2000-12-06
2004-05-11
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
Reexamination Certificate
active
06735706
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electronic devices and, more particularly, to programmable power management systems and methods.
2. Related Art
A typical electronic device, which includes one or more printed circuit boards that form a complex electronic system, requires multiple voltages for supplying power to numerous components. For example, the components may include a fan requiring 12 volts (V), memory devices requiring 2.5 V and 1.8 V, a microprocessor requiring 2.5 V and 1.8 V, analog circuits requiring 5 V, and logic devices requiring 5 V, 3.3 V, and 2.5 V. These components may further require a complex power-on or reset sequence that employs a timed, defined, reset signal. Additionally, many of these components cannot tolerate significant voltage swings or a power supply interruption and may require an interrupt or reset signal prior to powering down. Consequently, various portions of the printed circuit board or electronic system may require various voltages and a structured power up, power down, and reset sequence.
Failure to maintain the proper voltage level or to power down correctly may result in problems such as a static random access memory prematurely erasing required data or the entire system locking-up. A watchdog timer circuit may be required in case the system or processor locks-up in order to properly reset the system.
The system may also require thermal management to control the printed circuit board's thermal condition. For example, thermal management may control a fan speed based on temperature readings. Furthermore, the system may require a board level identification tag memory (e.g., a serial electrically erasable programmable read only memory) to identify and track the printed circuit board.
A conventional electronics system may monitor voltages, provide reset signals and power-loss warnings, or provide a watchdog circuit and battery backup switching. However, a drawback of conventional systems is that to perform these functions requires many discrete and specialized integrated circuits, which occupy valuable printed circuit board space. Furthermore, the identification tag memory along with the thermal management circuit, if these are included, are provided as stand-alone devices that occupy additional printed circuit board space and add to the size and complexity of the overall system.
Another drawback of these conventional systems is that generally there is no on-board logic for system control or sequencing. If programmable functions are permitted, it is only provided through resistor/capacitor networks that are external to the power management integrated circuits. Therefore, discrete components are required, additional board space is required, and limited control or options are provided. For example, the voltage, timing, polarity, and input/output signals are generally fixed or have limited versatility.
As a result, there is a need for a single device that will consolidate the functions of the various stand-alone power management devices and provide on-chip programmable functions.
SUMMARY OF THE INVENTION
In accordance with some embodiments of the present invention, programmable management systems and methods are provided that offer programmable voltage, current, and temperature diode monitoring capability having hysteresis and programmable thresholds and input filtering. An integrated CPLD allows user-defined power supply sequencing and generates reset and interrupt signals, system status, LED drive, and digital input and output signals, along with controlling a number of high-side FET drivers with soft turn-on capability. The programmable power management system integrates an internal oscillator, ID tag memory, serial interface (e.g., offering I
2
C, SPI, microwire, and ISP standards), along with programmable watchdog timer support, and monitors multiple system voltages such as 5 V, 3.3 V, 2.5 V, and 1.8 V operation. Non-volatile programming may be employed utilizing E
2
CMOS for such functions as thresholds and configurations, CPLD, tag memory, and status capture register.
The present invention described herein provides significant advantages over conventional power management integrated circuits. The programmable power management systems and methods, in accordance with some embodiments, integrate a number of functions into a single in-system programmable chip. The chip performs not only power management functions, but may also provide thermal management and board identification such as with a tag memory. The chip functions may include multiple voltage, current, and/or temperature monitoring or input window comparisons, internal voltage references, programmable timers, interrupt control, complete reset function for the chip and/or the system, battery backup control, low battery warning, de-bounced pin reset, integrated serial EEPROM, integrated comparator, and CPLDs.
The chip also allows on-chip programmability for functions such as programmable tolerances for over/under voltages, programmable reset polarity (e.g., high-low-open drain), programmable time delay for power-on reset (POR) sequence (e.g., on and off), programmable time delay for reset upon voltage drop, programmable output signal polarity, programmable open drain or open collector, programmable timer and time-out duration, programmable interrupt duration, programmable extended sleep mode/wakeup function, programmable memory (e.g., E
2
tag for board identification), programmable comparator, and CPLD logic. Thus, the programmable power management system and method may provide not only power management functions, but also thermal management, memory, and on-board logic for programmable functions such as system control or sequencing and accept or provide input/output signals that are versatile in terms such as voltage, timing, and polarity.
In accordance with an embodiment of the present invention, a programmable power management integrated circuit includes input terminals that receive analog input signals and programmable input/output terminals. A programmable logic circuit is coupled to a first group of input terminals and provides at least a reset signal, an interrupt signal, a status signal, or a control signal through the first group of input/output terminals. Analog input monitors, coupled to the input terminals, monitor voltage, current, and temperature signals and compare these signals to programmable thresholds, with the result provided to the programmable logic circuit. The integrated circuit may also include FET drivers, a serial interface, a capture register, an oscillator, a pre-scaler circuit, a temperature diode, an ISP/JTAG interface, a tag memory, and a capture register. The integrated circuit may be programmed through a graphical user interface having selectable screen displays corresponding to various programmable chip functions or values.
In accordance with another embodiment of the present invention, a programmable system management integrated circuit includes input terminals, which receive analog input signals, and programmable input/output terminals, which receive or provide digital signals. A programmable analog circuit is coupled to one or more of the input terminals and provides one or more output signals. A programmable logic circuit receives the output signals and provides its own output signals through the programmable input/output terminals.
A more complete understanding of the programmable management systems and methods will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.
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patent: 5721933 (1998-02-01), Walsh et al.
patent: 5742833 (1998-04-01), Dea et al.
patent: 5787294 (1998-07-01), Evoy
patent: 5872983 (1999-02-01), Walsh et al.
patent: 6601178 (2003-07-01), Gulick
Bennett James J.
Morse Douglas C.
Tomlinson Jock F.
Wilkinson David C.
Heckler Thomas M.
Lattice Semiconductor Corporation
MacPherson Kwok & Chen & Heid LLP
Michelson Greg J.
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