Programmable pin impedance reduction on multistandard...

Details Programmable pin impedance reduction on multistandard... Programmable pin impedance reduction on multistandard...

2007-07-03

2007-07-03

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S030000, C326S026000, C326S038000

Reexamination Certificate

active

11135254

ABSTRACT:
Programmable logic devices, such as field programmable gate arrays, may have input/output (I/O) circuitry that can be programmed for either differential or single-ended signaling. I/O pins coupled to such programmable I/O circuitry typically have high parasitic input pin capacitance during differential signaling. I/O pins may also have high parasitic input pin inductance. Additional impedance circuit elements such as capacitive or inductive devices are coupled in the programmable I/O circuitry to produce a compensatory impedance that reduces, if not substantially eliminates, the effects of the parasitic input pin capacitance and/or inductance during differential signaling.

REFERENCES:
patent: 6433579 (2002-08-01), Wang et al.
patent: 6480026 (2002-11-01), Andrews et al.
patent: 6625796 (2003-09-01), Rangasayee et al.
patent: 6700823 (2004-03-01), Rahman et al.
patent: 2006/0158223 (2006-07-01), Wang et al.
Thanachayanont, A., and Payne, A., “VHF CMOS integrated active inductor”, Electronics Letters vol. 32 No. 11, pp. 999-1000, May 23, 1996.

Affiliated with

Also associated with

Rating

Programmable pin impedance reduction on multistandard... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable pin impedance reduction on multistandard..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable pin impedance reduction on multistandard... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3803196