Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-07-26
2004-11-02
Le, Don (Department: 2816)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S027000, C326S083000
Reexamination Certificate
active
06812732
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to programmable parallel on-chip termination impedance and impedance matching, and more particularly, to parallel on-chip termination impedance and impedance matching circuits and methods.
Signal reflection on transmission lines can cause distortion that degrades the overall quality of the signal. To minimize signal reflection, transmission lines are resistively terminated. In the case of integrated circuits that are in communication with other circuitry on, for example, a circuit board, termination is often accomplished by coupling an external termination resistor (e.g., a 50 Ohm resistor) to the relevant input/output (I/O) pins.
A termination resistor is typically coupled to every I/O pin receiving an input signal from a transmission line. Often hundreds of termination resistors are needed for an integrated circuit. Numerous external termination resistors can consume a substantial amount of board space. The use of external components for termination purposes can be cumbersome and costly, especially in the case of an integrated circuit with numerous I/O pins.
It is therefore desirable to provide on-chip termination impedance to eliminate the need for the external components. It is further desirable to make such on-chip termination impedance insensitive to process, supply voltage, and temperature (PVT) variations.
BRIEF SUMMARY OF THE INVENTION
The present invention provides efficient, flexible, and cost-effective on-chip parallel termination impedance. According to the present invention, termination transistors can provide parallel termination impedance to I/O pins on an integrated circuit. The impedance of the termination transistors is programmably adjustable. The impedance of the termination transistors can be programmed to meet different input/output standards.
The present invention also provides impedance matching circuitry. The impedance matching circuitry can match the impedance of the termination transistors to the impedance of external (off-chip) reference resistors. A user can change the impedance of the reference resistors to alter the impedance of the termination transistors. Thus, the impedance matching circuitry makes the termination transistors programmable.
A pair of external reference resistors can be used to control the parallel termination impedance provided to a large number of I/O pins on an integrated circuit. The present invention therefore eliminates the need for external components that are used to provide parallel termination impedance.
REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 5164663 (1992-11-01), Alcorn
patent: 5359235 (1994-10-01), Coyle et al.
patent: 5374861 (1994-12-01), Kubista
patent: 5726583 (1998-03-01), Kaplinsky
patent: 5764080 (1998-06-01), Huang et al.
patent: 5864715 (1999-01-01), Zani et al.
patent: 5955911 (1999-09-01), Drost et al.
patent: 5970255 (1999-10-01), Tran et al.
patent: 6008665 (1999-12-01), Kalb et al.
patent: 6026456 (2000-02-01), Ilkbahar
patent: 6037798 (2000-03-01), Hedberg
patent: 6049255 (2000-04-01), Hagberg et al.
patent: 6064224 (2000-05-01), Esch, Jr. et al.
patent: 6087847 (2000-07-01), Mooney et al.
patent: 6100713 (2000-08-01), Kalb et al.
patent: 6147520 (2000-11-01), Kothandaraman et al.
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6329836 (2001-12-01), Drost et al.
patent: 6362644 (2002-03-01), Jeffery et al.
patent: 6414512 (2002-07-01), Moyer
patent: 6433579 (2002-08-01), Wang et al.
patent: 6586964 (2003-07-01), Kent et al.
patent: 6590413 (2003-07-01), Yang
patent: 6603329 (2003-08-01), Wang et al.
patent: 6639397 (2003-10-01), Roth et al.
patent: 6642741 (2003-11-01), Metz et al.
patent: 2002/0010853 (2002-01-01), Trimberger et al.
patent: 2002/0060602 (2002-05-01), Ghia et al.
patent: 2002/0101278 (2002-08-01), Schultz et al.
patent: 2003/0062922 (2003-04-01), Douglass et al.
patent: 2004/0008054 (2004-01-01), Lesea et al.
Altera, Apex 20K “Programmable Logic Device Family,” Altera Corporation, Ver. 1.1, May 2001.
Altera, Apex II “Programmable Logic Device Family,” Altera Corporation, Ver. 1.1, May 2001.
Esch and Manley, Theory and Design of CMOS HSTL I/O Pads, The Hewlett Packard Journal, Aug. 1998.
Xilinx, “Virtex-II 1.5V Field Programmable Gate Arrays,” Xilinx, DSO3102 (v1.5), Apr. 2, 2001.
Bendak, M. et al. (1996). “CMOS VLSI Implementation of Gigabyte/second computer network links,” Dept. of Electrical and Computer Engineering University of California at San Diego, La Jolla, CA 92093-0407,IEEE International Symposium on Circuits and Systemspp. 269-272.
Boni, A. et al (2001). “LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-um CMOS,” IEEE Journal of Solid-State Circuits, 36(4):706-711.
Xilinx, “Spartan-3 1.2V FPGA Family: Functional Description,” Xilinx, DS099-2 (vt.2) Jul. 11, 2003.
Xilinx, “Virtex-II Platform FPGAs: Detailed Description,” Xilinx, DS031-2 (v.3 1) Oct. 14, 2003.
Xilinx, “Virtex-II Pro Platform FPGAs: Functional Description,” Xilinx, DS083-2 (v2.9) Oct. 14, 2003.
Altera Corporation
Cahill Steven J.
Le Don
Townsend and Townsend / and Crew LLP
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