Programmable page table access

Details Programmable page table access Programmable page table access

2001-07-13

2004-04-27

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S202000, C711S203000, C711S207000

Reexamination Certificate

active

06728859

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of memory management within a computing system, and more particularly to an apparatus and method that extends the capabilities of a software-controlled virtual memory management unit such that a programmable mechanism is provided for accessing page tables in memory of varying configurations in addition to providing compatibility with page table structures prescribed by legacy operating system software.
2. Description of the Related Art
Virtual memory management techniques were developed during the mid-1970's specifically to address a number of problems experienced in early computing systems related to the execution of programs from memory and the storage of data associated with program execution. Virtual memory management is typically accomplished by providing a memory management unit (MMU) within a computing processing unit (CPU) that serves as an intermediary between address generation logic in the CPU and memory access logic. Under a virtual memory management scheme, application program instructions cause virtual addresses to be generated by the address logic. The MMU then translates the virtual addresses into physical addresses according to a predefined and configurable memory mapping strategy. The physical addresses are used by the access logic in the CPU to access locations in system memory. Virtual memory management techniques enable the operating system of a computing system to effectively control where application programs are loaded and executed from memory, in addition to providing a means whereby memory can be allocated to a program while it is executing and then released back into the memory pool when the memory is no longer required.
Almost all present day virtual memory techniques divide a CPU's address space into equal-sized blocks called memory pages. Allocating memory to programs in these equal-sized memory pages minimizes fragmentation effects and decreases the number of virtual address bits that must be translated. To access a memory page only requires translation of the upper bits of a virtual address; the lower bits of the virtual address are not translated and merely provide an offset into a memory page. The virtual-to-physical address mapping information, along with other information specifying the attributes (e.g., access protection features) of memory pages, are stored in a designated area of memory known as a page table. Entries within the page table are of a fixed size (i.e., number of bytes) and structure (i.e., single-level lookup table, multi-level lookup table).
Since each generated address in a virtual memory scheme must be translated, and since page tables are frequently accessed, associated page table access logic is directly in the critical timing path of a CPU. Accordingly, elements of the page table access logic are designed to be extremely fast and efficient, providing only those functions that are essential to accessing entries within the fixed page table structure.
Virtual memory management techniques are extremely powerful, but because of the overhead associated with the generation of every virtual address, employment of these techniques has not migrated into application areas that comprise a few, relatively small, embedded application programs executing on a CPU. Hence, present day MMU designs provide for page tables structures that are commensurate with numerous, medium to large application programs executing, say, on a desktop system or workstation. It is quite uncommon today to find page tables in a virtual memory system that are smaller than 4 KB in structure and that have less than 4-byte entries.
Recent advances in device scaling and fabrication, however, are now enabling manufacturers to provide CPU designs that can absorb the timing and area overhead associated with address translation and corresponding page table accesses, thus opening up virtual memory management as an option to the embedded processing world. Yet, while virtual memory management provide advantages to embedded applications, it is a well known fact that size, cost, and power constraints generally imposed on embedded processing systems result in designs whose memory use must be controlled more stringently than their larger and more costly counterparts.
Accordingly, there is a need in the art for virtual memory management techniques and methods that provide for page table structures that are smaller than 4 KB and that have page table entries that are less than 4-bytes in size.
In addition, there is a need to for virtual memory management techniques that provide for configurable page table accesses according to the structure of associated page tables
Furthermore, to retain existing customer bases for current virtual memory products, there is a need for these upgraded/improved virtual memory management products to preserve compatibility with legacy memory management software.
SUMMARY OF THE INVENTION
The present invention provides a superior technique for extending the capabilities of existing memory management systems to provide for programmable page table accesses, while at the same time retaining compatibility of these systems with operating system software that implements legacy memory management protocols.
In one embodiment, an apparatus in a virtual memory system is provided to enable programmable page table access. The apparatus includes context logic and context configuration logic. The context logic designates a data structure associated with a block of virtual memory. The context logic has a plurality of fields. Each of the plurality of fields provides part of a pointer to the data structure. The context configuration logic is coupled to the context logic. The context configuration logic prescribes the structure of the each of the plurality of fields, where programming the context configuration logic determines the function by which the context logic derives a useful value from a virtual address associated with an event.
One aspect of the present invention features a virtual memory management apparatus for providing programmable page table access. The virtual memory management apparatus includes context logic and context configuration logic. The context logic designates a data structure associated with a block of virtual memory. The context logic has a base field, an offset field, and a zero field. The base field, for indicates a base address of the data structure. The offset field is coupled to the base field, and indicates an offset within the data structure corresponding to an entry within the data structure. The zero field is coupled to the offset field. The number of bits within the zero field corresponds to the size of the entry. The context configuration logic is coupled to the context logic. The context configuration logic prescribes the size of the base field, the size of the offset field, and the size of the zero field, wherein the relationship between a virtual address associated with an event and a data structure entry pointer generated by the context logic is specified by programming.
Another aspect of the present invention contemplates a computer program product for use with a computing device. The computer program product includes a computer usable medium, having computer readable program code embodied in the medium, for causing an apparatus in a virtual memory system to be described that provides programmable page table access. The computer readable program code includes first program code and second program code. The first program code describes context logic. The context logic designates an entry within a data structure associated with a block of virtual memory. The context logic has a plurality of fields. Each of the plurality of fields provides part of a pointer to the entry. The second program code is coupled to the first program code. The second program code describes context configuration logic. The context configuration logic prescribes the structure of the each of the plurality of fields, where programming the context c

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