Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-05-01
2004-03-23
Cho, James H (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C333S017300
Reexamination Certificate
active
06710618
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to on-chip termination resistors and more specifically to a programmable on-chip termination device.
BACKGROUND OF THE INVENTION
The Low Voltage Differential Swing (LVDS) standard provides a data interface that has a balanced I/O buffer driver that sends data by current signaling in a balanced interconnect environment. LVDS is adapted for high-speed transmission of binary data over copper. An advantageous aspect of LVDS is provided due to the response of LVDS receivers to differential voltages, thus LVDS receivers are fairly immune to noise and emit less electromagnetic interference (EMI) than other data transmission standards.
A problem associated with LVDS compliant interfaces is a requirement of a precise line termination resistance. A line termination resistance, fabricated according to various methods, is typically placed in front of a LVDS receiver to maintain signal quality and integrity. LVDS circuits must provide buffers to ensure a signal current of typically 4.0 milliAmperes on a voltage drop across the on-chip resistance of typically 400 millivolts. In order to provide a resistor termination to an LVDS transmission line that does not suffer symmetrical signal distortion, an on-chip resistance must be of a chosen value and remain within a desired tolerance. The chosen value for the termination resistor may be required to be between 50 Ohms and 150 Ohms to suit the characteristic impedance of the media with a tolerance of ±10%. However, due to temperature and technology variations, an on-chip resistance may vary as much as 30%. Consequently, a programmable on-chip resistance capable of providing an adjustable resistance while accommodating process and temperature variation is desirable.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method and apparatus for producing a programmable on-chip resistance. In an embodiment of the invention, a programmable on-chip resistance is maintained to provide a constant resistance for differential input common mode voltage changes. Further, a programmable on-chip termination device may provide a constant resistance over changes in an amplitude of an input differential swing. The programmable on-chip resistance may be implemented through a single transistor in which a control voltage for altering the resistance of the transistor is produced by the use of an intermediate termination device. The intermediate termination device may replicate the programmable on-chip termination device to ensure proper adjustment to maintain a constant resistance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 6424169 (2002-07-01), Partow et al.
patent: 6509765 (2003-01-01), Drost
patent: 6545522 (2003-04-01), Mughal et al.
patent: 6552565 (2003-04-01), Chang et al.
patent: 03212701 (1991-09-01), None
Cho James H
Cypress Semiconductor Corp.
Marger & Johnson & McCollom, P.C.
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