Programmable non-volatile semiconductor memory device

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S100000, C365S225700, C365S185210

Reexamination Certificate

active

07102910

ABSTRACT:
The present invention relates to a programmable non-volatile semiconductor memory device comprising a matrix of rows and columns of memory cells (1). To reduce the required memory area a 3T memory cell is proposed comprising a bridge of two bridge transistors (MN0,MN1), preferably NMOS transistors, a read transistor, preferably an PMOS transistor, and a silicided polysilicium fuse resistor (R). The read transistors enable the use of a single sense line (SL) for all memory cells (1) of the same row or column in the matrix thus enabling the use of a common sense amplifier for sensing memory cells (1).

REFERENCES:
patent: 6859382 (2005-02-01), Rinerson et al.
patent: WO 2002/43152 (2001-11-01), None
patent: WO 2002/052647 (2001-12-01), None

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