Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1999-02-17
2000-07-25
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Bad bit
36523006, G11C 2900
Patent
active
060943831
ABSTRACT:
A programmable non-volatile memory device has a plurality of rows of memory cells that are accessible through selection addresses, with the number of physical rows being greater than the number of rows that are addressable at a given time. An associating circuit associates selected physical rows of the memory device with selection addresses. The associating circuit includes an associative memory that has a programmable memory location for each physical row of the memory device, and each memory location in the associative memory has an address field and at least one state bit. In one preferred embodiment, in the read mode, a row of the memory device is selected when the corresponding memory location in the associative memory contains the received address and state bits indicating that the row stores valid data for the received address. A method of programming such a non-volatile memory device is also provided.
REFERENCES:
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5604702 (1997-02-01), Tailliet
patent: 5677883 (1997-10-01), Miwa
French Search Report dated Nov. 6, 1998 with annex on French Application No. 98-02221.
Galanthay Theodore E.
Le Vu A.
STMicroelectronics S.A.
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