Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-14
2002-06-18
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S319000, C257S350000, C257S351000
Reexamination Certificate
active
06407425
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a single polysilicon neuron MOSFET on SOI. The described single polysilicon neuron MOSFET has synaptic learning capability without the cross-talk noise and leakage current associated with conventional neuron MOSFETs.
BACKGROUND OF THE INVENTION
Technologies capable of implementing intelligence on an integrated circuit hardware level is rapidly emerging as a key enabling step for the development of the next generation low-power self-sufficient portable systems and products. These technologies, which contain devices known as evolvable hardware, have been the focus of new efforts to develop autonomous, adaptive and fault tolerant electronic systems with the capability to learn and self-adjust depending on the environment and algorithm used for the new product applications. One of the most promising technologies for achieving these goals is known as the neuron MOSFET.
FIG. 1
shows a circuit schematic of a neuron MOSFET with n capacitively coupled inputs
115
-
1
,
115
-
2
, . . . and
115
-n, to the floating gate
100
. The source
110
and the drain
105
of the transistor are also represented in FIG.
1
. Each capacitively coupled input has a capacitance associated with it given by C
1
, C
2
, . . . , and C
n
for the inputs
115
-
1
,
115
-
2
, . . . , and
115
-n respectively. Defining a total capacitance C
TOT
as
C
TOT
=
∑
i
=
0
n
C
i
(
1.1
)
a Factor Z can be determined as
Z
=
∑
i
=
0
n
W
i
V
i
>
V
TH
-
(
C
o
/
C
TOT
)
V
o
-
Q
F
/
C
TOT
(
1.2
)
where
W
i
=C
i
/C
TOT
Equation 1.1 means that the value of the linear sum of all input voltages to the gates
115
-
1
,
115
-
2
, . . . , and
115
-n weighted by W
1
, W
2
, . . . , and W
n
becomes larger than V
TH
* given by Eq. (1.3), the device turns on and the source
110
and drain
105
are connected. See U.S. Pat. No. 5,258,657 of Shibata et al.
V
TH
*=V
TH
−(
C
o
/C
TOT
)
V
o
−Q
F
/C
TOT
(1.3)
where C
o
is the capacitance between the floating gate and the substrate and Q
F
is the charge on the floating gate. Because the neuron MOSFET sums the input voltages and the output condition is dependent on this sum being greater than the threshold voltage of the MOSFET, the device behaves similar to a biological neuron. The neuron MOSFET offers advantages for both digital and analog applications since the input signals can be isolated from the biasing networks. This allows for significant advantages when designing analog circuits for low power applications.
Prior Art on forming neuron MOSFETs has focused on bulk silicon using the following two basic approaches. The dual polysilicon process typically found in technologies developed for EEPROM applications is described in the U.S. Pat. No. 5,258,657 of Shibata et al. and the single-gate polysilicon process described in the U.S. Pat. No. 5,895,945 of Pan et al. Although both of these approaches are successful in making neuron MOSFETs, they have some severe limitations regarding manufacturability of the devices. especially for analog applications. Some of the limitations of these two approaches will now be discussed. In the case of the dual-polysilicon process, there is difficulty in achieving matching in the neuron MOSFETs and uniformity in device characteristics from die to die, wafer to wafer, and lot to lot. Mismatch issues arise due to two key issues: (a) the dual polysilicon processing of these devices, which includes etching variations and doping variations, and (b) due to capacitive coupling to the substrate of the devices. The devices are sensitive to cross-talk noise effects since the neuron MOSFETs in bulk technology are capacitively coupled to all other devices through the substrate. This effect tends to worsen as technologies are scaled unless expensive triple well processes are used. Programming voltages and currents can reach the active neuron MOSFET through diode junction breakdown and leakage, which can cause reliability or device degradation issues in the active neuron MOSFET. This occurs in the programming structure of the neuron MOSFET that typically use junction isolated EEPROM technologies. To help eliminate some of these problems (reduce the programming voltages) dual gate oxide processes tend to be used adding cost and complexity to the technology. As pointed out above, because of the junction isolation, there can be a loss in the programming current to the substrate of the technologies hence requiring higher programming voltages or currents than necessary for actual device programming. Higher temperature limitations on the devices also occur due to leakage currents. The devices are susceptible to single-event-upset effects and are potentially susceptible to latch-up effects during programming of the neuron MOSFET and finally, polysilicon/polysilicon capacitors have lower capacitance per unit area than gate-oxide capacitors and thus will require more area than a single-polysilicon process for building neuron MOSFET cells.
For the case of bulk silicon single-polysilicon processes the devices are more sensitive to cross-talk noise effects than the case of the dual polysilicon process since the floating gate in more exposed to substrate capacitance than in the of the dual polysilicon process where the floating gate and the input coupling capacitors can be placed over LOCOS or shallow trench isolation regions. Programming voltages and currents can reach the active neuron MOSFET and can cause reliability or device degradation issues. Similar to the dual polysilicon process, this occurs through diode junction breakdown and leakage. Because of the increased junction area in the single polysilicon neuron MOSFET, the high temperature limitations due to leakage currents become more severe in the single polysilicon process than in the dual polysilicon process. These devices are also more susceptible to single-event-upset effects than the dual polysilicon process due to increased junction areas. As the bias applied to the device changes, the depletion capacitance to the substrate changes. This changes the total capacitance C
TOT
the above equations and therefore introduces a parasitic non-linearity in the device operating characteristics. Ideally, neuron device operation is linear with respect to the input voltage. Significant parasitic capacitances exist in this technology through the substrate depletion capacitances thereby affecting device performance through device speed and area of devices required to achieve a given resolution or accuracy in the neuron MOSFET behavior.
There is therefore a need for a neuron MOSFET that overcomes that above described limitations of the existing dual polysilicon neuron MOSFET and the single gate neuron MOSFET.
SUMMARY OF INVENTION
The instant invention describes a single polysilicon neuron MOSFET architecture with synaptic learning capability. The structure described is unique to silicon-on-insulator (SOI) substrates and comprises a single polysilicon layer gate structure. In addition, the neuron MOSFET structure of the instant invention has a number of doped regions completely isolated from each other by a number of isolation structures. The structure comprises a contiguous conductive film formed over the MOS transistor region forming a transistor floating gate and other regions of said contiguous conductive film positioned over a number of the doped regions to form input capacitor structures to the neuron MOSFET.
The design of the instant invention allows for the rapid learning (FN programming) or for long term learning (hot-electron programming) without impacting the active region of the neuron MOSFET or other devices on the chip. Other technical advantages will be readily apparent to one skilled in the art from the following FIGURES, description, and claims.
REFERENCES:
patent: 5258657 (1993-11-01), Shibata et al.
patent: 5633520 (1997-05-01), Wu et al.
patent: 5806054 (1998-09-01), Bergemont et al.
patent: 5895945 (1999-04-01), Pan et al.
Babcock Jeffrey A.
Balster Scott G.
Howard Gregory E.
Pinto Angelo
Steinmann Philipp
Brady III W. James
McLarty Peter K.
Ngo Ngan V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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