Programmable multi-standard I/O architecture for FPGAS

Details Programmable multi-standard I/O architecture for FPGAS Programmable multi-standard I/O architecture for FPGAS

2005-06-21

2005-06-21

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S083000, C326S087000

Reexamination Certificate

active

06909306

ABSTRACT:
The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards.

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