Programmable memory verify "0" and verify "1" circuit and method

Details Programmable memory verify "0" and verify "1" circuit and method Programmable memory verify "0" and verify "1" circuit and method

1996-07-19

1998-02-03

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518521, G11C 1134

Patent

active

057151954

ABSTRACT:
A method for automatically detecting and correcting the underprogramming of a memory cell 10 in a non-volatile, progrommable memory array 1, the array having a plurality of such cells, each such cell being programmable by a progromming step that stores charge therein and being erasable by an erasing step that removes charge therefrom, and each such cell being readable to determine whether such cell is in a progrommed state or in an erased state. First, charge is stored in a selected cell therein 74. Then the selected cell is read to determine whether the selected cell is programmed 78. If the step of reading does not determine such cell to be programmed 80, the steps of storing and reading are automatically repeated until either the step of sensing indicates a sufficiently programmed cell or, alternatively, until a predermined number of iterations of the steps has been performed 86.

REFERENCES:
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5570315 (1996-10-01), Tanaka et al.

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