Programmable memory transistor

Details Programmable memory transistor Programmable memory transistor

2002-12-19

2004-07-13

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S321000, C257S322000

Reexamination Certificate

active

06762453

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
Not applicable.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention generally relates to semiconductor devices. More particularly, this invention relates to a programmable memory transistor having a floating gate that exhibits improved voltage retention.
(2) Description of the related art
Programmable memory transistors (PMT), including electrically programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices, are a type of insulated gate field effect transistor (IGFET) having nonvolatile memory. As used in the art, “nonvolatile” refers to the retention of memory without the need of a power source, here by trapping a charge on a “floating” gate disposed above the IGFET channel region and typically below a conventional control gate electrode, such that the control and floating gates are “stacked.” The floating gate is described as “floating” because it is electrically insulated from the channel region by a gate oxide, typically insulated from the control gate by a “tunnel” oxide, and not directly accessed by any electrical conductor. PMT's can be electrically programmed after manufacture by placing an electrical charge on the floating gate by the effects of tunneling or avalanche injection from the control gate electrode through the tunnel oxide. Once an electrical charge is placed on the floating gate, the charge is trapped there until it is deliberately removed, such as by exposure to ultraviolet light. The trapped charge on the PMT floating gate raises the threshold voltage of the underlying channel region of the IGFET, thus raising the “turn on” voltage of the IGFET to a value above the voltage otherwise required for the IGFET. Accordingly, the IGFET stays “off” even when a normal turn-on voltage is applied to its control gate electrode.
Stacked control and floating gates require two separate conductor layers, typically polysilicon, resulting in a double-polysilicon (“Poly1/Poly2”) device structure. PMT's are typically fabricated in the same semiconductor substrate as MOS (metal-oxide-semiconductor) transistors, which are single-polysilicon layer structures and therefore require fewer patterning steps than PMT's. Therefore, PMT's have been proposed that make use of a single polysilicon layer, such as that disclosed in U.S. Pat. No. 6,324,097. An example of another single-polysilicon PMT is shown in
FIG. 1
, in which a PMT
110
is fabricated on a semiconductor substrate
112
doped with an N-type impurity. A P-well
114
is formed in a surface region of the substrate
112
, and divided by a field oxide
116
into two active regions. An NMOS transistor
118
is formed in one of the active regions and conventionally includes source and drain regions
120
and
122
in the P-well
114
, a channel
124
between the source and drain regions
120
and
122
, and a gate electrode
126
separated from the channel
124
by a gate insulator
128
(e.g., silicon dioxide). Source and drain metal
130
and
132
make ohmic contact with the source and drain regions
120
and
122
, respectively. The gate electrode
126
of the NMOS transistor
118
is a floating gate, in that it is not directly connected to a gate metal or other conductor. Instead, the gate electrode
126
is defined by a single polysilicon layer that also defines a second floating gate
146
of a control gate structure
138
fabricated in the second active region of the substrate
112
(on the right-hand side of FIG.
1
). The control gate structure
138
represented in
FIG. 1
includes two N+ contact diffusions
142
within an N-well
144
(though a single contact diffusion
142
or more than two contact diffusions
142
could be present). The N-well
144
serves as the control gate of the control gate structure
138
, effectively replacing the second polysilicone layer of a conventional double-polysilicon PMT. The control gate (N-well)
144
is separated from the second floating gate
146
by a gate oxide
148
, creating what is effectively a coupling capacitor. A control gate metal
150
contacts the N+ contact diffusions
142
to provide ohmic contact with the control gate
144
.
When programming the prior art PMT
110
, an electrical charge is placed on the floating gate
126
of the NMOS transistor
118
by the effect of tunneling or avalanche injection from the channel
124
of the gate electrode
126
through the gate insulator
128
to the floating gate
126
. For this purpose, a sufficiently high potential must be applied to the control gate metal
150
to capacitively induce a charge in the floating gate
146
as well as the floating gate
126
as a result of the gates
126
and
146
being formed of the same polysilicon layer. Simultaneously, the drain region
122
is biased at a high voltage level while the source region
120
and substrate
112
are electrically connected to ground, so that electrons are ejected from the drain region
122
through the gate insulator
128
into the floating gate
126
.
Because of the large interfacial barrier energy provided by the gate insulator
128
, a charge stored onto the floating gate
126
has a long intrinsic storage time. For PMT's of the type shown in
FIG. 1
, the measured mean decay of a stored potential (Vth) may be about 0.2V/decade-hours at 160° C. Assuming an initial programmed mean Vth of about 8V, it would require about 10
21
years for the PMT to discharge to a Vth of 3V. At the end of ten years, the leakage would have dropped to an average of one electron per day. Vth degradation in the PMT
110
is the result of and limited by physical processes. The magnitudes of the electric field and temperature dictate what conduction processes will be dominant. There are three distinct phases of Vth degradation for nominal PMT's, each associated with a different possible physical mechanism of charge distribution/conduction and each having its own empirical “activation energy.” First there is an initial period of rapid Vth loss, which is believed to be associated with the depolarization/dielectric absorption behavior observed to a lesser or greater degree in all capacitor dielectrics. Second, there is an intermediate period of charge loss associated with a high (but less than 6 Mvolt/cm, where Fowler-Nordheim tunneling is dominant) but decaying electric field. It is possible that there is movement of trapped electrons during this intermediate period, which has an “activation energy” of about 0.2 eV. Ultimately, there is a long period of low field leakage through the gate insulator. The low field conduction mechanism is generally accepted as being conduction by thermionic emission.
When subjected to elevated temperatures, e.g., 160° C. or more, PMT's experience a significant initial drop in Vth attributed to the first degradation phase noted above. Thereafter, Vth stabilizes, though continuing to drop at a much lower rate attributed to the second and third degradation phases noted above. This lower rate is sufficiently low to permit the reliability of the device to be judged based on the initial Vth drop. Accordingly, PMT's typically undergo a data retention bake, or stress test, that involves baking at a sufficiently high temperature to cause the initial drop in Vth. A PMT is deemed to have passed the stress test if its Vth has not dropped below a predetermined level at the completion of the high temperature bake.
From the above, it can be appreciated that PMT's capable of exhibiting more stable Vth, corresponding to improved reliability and memory retention time, would be desirable. It would also be desirable to eliminate the requirement for a stress test to ascertain reliability of a PMT.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a programmable memory transistor (PMT) that exhibits significantly better performance in terms of charge retention and reliability. The PMT of this invention is able to make use

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