Programmable memory device having programming current absorbing

Details Programmable memory device having programming current absorbing Programmable memory device having programming current absorbing

1991-08-28

1993-12-07

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

36518905, 36523008, G11C 1130

Patent

active

052688640

ABSTRACT:
A programmable memory device includes memory cells arranged at cross points of word lines and bit lines, a selecting part for selectively decreasing potentials of the word lines, and a writing part for selectively supplying programming currents to the memory cells via the bit lines. Programming current absorbing transistors have first terminals respectively connected to the word lines, second terminals set at a predetermined potential, and bases, and a common load element connected between a node and a programming voltage line. A plurality of base current supplying circuits, which are respectively coupled to the programming current absorbing transistors and connected in common to the node, turn ON the programming current absorbing transistors related to word lines selected by the selecting part so that base currents pass from the programming voltage line to the bases of the programming current absorbing transistors via the common load element and the base current supplying circuits.

REFERENCES:
patent: 4953127 (1990-08-01), Nagahashi et al.
Patent Abstracts of Japan, vol. 14, No. 183 (P-1035) Apr. 12, 1990 & JP-A-029998 (NEC Corp) Jan. 31, 1990.
Patent Abstracts of Japan, vol. 14, No. 321 (P-1074) Jul. 10, 1990 & JP-A-2 105395 (NEC Corp) Apr. 7, 1990.

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