Programmable memory decode circuits with transistors with...

Details Programmable memory decode circuits with transistors with... Programmable memory decode circuits with transistors with...

2000-05-31

2001-04-17

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S200000, C257S302000, C257S315000

Reexamination Certificate

active

06219299

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits and in particular to programmable memory address and decode circuits with transistors having vertical gates.
BACKGROUND OF THE INVENTION
One difficulty with memory address and decode circuit transistors is the one time programmability of the metal oxide semiconductor field effect transistors (MOSFETs) used in such a conventional array. Another difficulty is that when floating gate transistors are used to afford in the field, or in service programmability to the array such floating gate transistors generally require high operating and high programming voltages which are not well suited to low power applications. These floating gate transistors can be EEPROM, EAPROM, and flash memory cell types. One reason for the high operating and high programming voltage requirements in these floating gate transistors is the adverse capacitance ratio between the control gate and the floating gate. In other words, the capacitance between the control gate to floating gate (CCG) is about the same as the floating gate to substrate capacitance (CFG).
FIG. 1A
is an illustration of a horizontal EEPROM, EAPROM, or flash memory device formed according to the teachings of the prior art. As shown in
FIG. 1A
, conventional horizontal floating gate transistor structures include a source region
110
and a drain region
112
separated by a channel region
106
in a horizontal substrate
100
. A floating gate
104
is separated by a thin tunnel gate oxide
105
shown with a thickness (t1). A control gate
102
is separated from the floating gate
104
by an intergate dielectric
103
shown with a thickness (t2). Such conventional devices must by necessity have a control gate
102
and a floating gate
104
which are about the same size in width.
FIG. 1B
is an illustration of a vertical EEPROM, EAPROM, or flash memory device formed according to the disclosure in a co-pending, commonly assigned application by W. Noble and L. Forbes, entitled “Field programmable logic array with vertical transistors,” Ser. No. 09/032,617, filed Feb. 27, 1998.
FIG. 1B
illustrates that vertical floating gate transistor structures have a stacked source region
110
and drain region
112
separated by a vertical channel region
106
. The vertical floating gate transistor shown in
FIG. 1B
further includes a vertical floating gate
104
separated by a thin tunnel gate oxide
105
from the channel region
106
. A vertical control gate
102
is separated from the floating gate
104
by an intergate dielectric
103
. As shown in
FIG. 1B
, the vertical control gate
102
and the vertical floating gate
104
are likewise about the same size in width relative to the channel region
106
.
Conventionally, the insulator, or intergate dielectric,
103
between the control gate
102
and the floating gate
104
is thicker (t2) than the gate oxide
105
(t1) to avoid tunnel current between the gates. The insulator, or intergate dielectric,
103
is also generally made of a higher dielectric constant insulator
103
, such as silicon nitride or silicon oxynitride. This greater insulator thickness (t2) tends to reduce capacitance. The higher dielectric constant insulator
103
, on the other hand, increases capacitance. As shown in
FIG. 1C
, the net result is that the capacitance between the control gate and the floating gate (CCG) is about the same as the gate capacitance of the thinner gate tunneling oxide
105
between the floating gate and the substrate (CFG). This undesirably results in large control gate voltages being required for tunneling, since the floating gate potential will be only about one half that applied to the control gate.
As design rules and feature size (F) in floating gate transistors continue to shrink, the available chip surface space in which to fabricate the floating gate also is reduced. In order to achieve a higher capacitance between the control gate and floating gate (CCG) some devices have used even higher dielectric constant insulators between the control gate and floating gate. Unfortunately, using such higher dielectric constant insulators involves added costs and complexity to the fabrication process.
Therefore, there is a need in the art to provide field programmable memory address and decode circuits which can operate with lower control gate voltages and which do not increase the costs or complexity of the fabrication process. Further such devices should desirably be able to scale with shrinking design rules and feature sizes in order to provide even higher density integrated circuits.
SUMMARY OF THE INVENTION
The above mentioned problems with field programmable memory address and decode circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Structures and methods for field programmable memory address and decode circuits are provided with logic cells, or floating gate transistors, which can operate with lower applied control gate voltages than conventional field programmable memory address and decode circuits. The field programmable memory address and decode circuits of the present invention do not increase the costs or complexity of the fabrication process. These circuits and methods are fully scalable with shrinking design rules and feature sizes in order to provide even higher density integrated circuits. The total capacitance of the logic cells within the field programmable memory address and decode circuits is about the same as that for the prior art of comparable source and drain spacings. However, according to the teachings of the present invention, the floating gate capacitance in the logic cells is much smaller than the control gate capacitance such that the majority of any voltage applied to the control gate will appear across the floating gate thin tunnel oxide. Thus, the logic cells in the programmable memory address and decode circuits of the present invention can be programmed by tunneling of electrons to and from the silicon substrate at lower control gate voltages than is possible in the prior art.
In one embodiment of the present invention an address decoder for a memory device is provided. The address decoder includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number logic cells that are disposed at the intersections of output lines and address lines. Further, a number of non volatile memory cells are disposed at the intersections of the address lines and at least one output line. In one embodiment, the at least one output line includes a redundant output line. According to the teachings of the present invention, the number of non volatile memory cells include a source region, a drain region, and a channel region separating the source and the drain regions in a horizontal substrate. A first vertical gate is located above a portion of the channel region and separated from the channel region by a first thickness insulator material. A second vertical gate is located above another portion of the channel region and separated therefrom by a second thickness insulator material. The second vertical gate opposes the first vertical gate, and is separated from the first vertical gate by an intergate dielectric.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4051354 (1977-09-01), Choate
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4962327 (1990-10-01), Iwazari
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5386132 (1995-01-01), Wong
patent: 5583360

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