Programmable memory controller

Details Programmable memory controller Programmable memory controller

1998-09-17

2002-04-02

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C365S230030, C365S233100

Reexamination Certificate

active

06366989

ABSTRACT:

BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to accessing the primary memory of a computer. More particularly, this invention relates to a technique for improving the interface to a primary memory by providing speed independence between a processor bus and the memory.
BACKGROUND OF THE INVENTION
Computer systems have a central processing unit (CPU) and a memory. When a CPU accesses memory, the memory responds within a certain period of time, referred to as latency response time. When memory is directly connected to the CPU via a system bus, the CPU often must wait for the memory to retrieve or store the data before continuing to execute the next instruction. To reduce the latency between the CPU and the memory, computer systems can use memory controllers as an interface between the CPU and the memory.
Three dimensional graphics and multimedia applications require fast execution. Target performance goals are ever-increasing and handling of multiple real-time audio and video streams simultaneously poses architectural challenges beyond pure computational capacity. To support an interactive graphics environment with real-time constraints, multiple high-bandwidth data streams must be managed efficiently and with low latency response time.
Memories respond to commands—typically read and write commands to retrieve and store data. When the memory controller accesses the memory with a command, the memory controller waits for the command to complete before outputting the next command. Waiting for each command to complete before outputting the next command takes a certain amount of time.
Synchronous dynamic random access memories (SDRAMs) offer improved latency response time and are available in various sizes. Different applications require different types and configurations of SDRAMs. SDRAMs operate at a much slower speed than that of the system bus.
In view of the foregoing, it would be highly desirable to improve computer system performance by reducing the latency between the CPU and memory by providing an interface to the CPU that operates independent of the SDRAM speed. It would also be highly desirable to provide a memory controller that can be programmed to support multiple arrays of SDRAMs, different types of SDRAMs, different SDRAM configurations and different clock frequencies. It would also be highly desirable to improve computer system performance by integrating a memory controller on a single die with the central processing unit to further improve the speed of transactions between the CPU and memory controller.
SUMMARY OF THE INVENTION
A synchronous dynamic random access memory controller has a high speed interface and a low speed interface. The high speed interface has a buffer with entries for receiving transactions, and the buffer has a valid bit for each entry. The entries store transactions that are received from a high speed bus. The low speed interface retrieves transactions from the buffer. The high speed interface and low speed interface each have state machines that synchronize the high speed and low speed interfaces using the valid bit for each of the entries.
The invention realizes improved computer system performance by providing a high speed interface and low speed interface. Each interface has state machines that operate independently of each other and are synchronized via a “valid” bit. By providing independent state machines, the memory controller reduces the time between consecutive transactions and thus reduces the latency response time.
In addition, the memory controller is programmable to support multiple arrays of SDRAMs, different types of SDRAMs, different SDRAM configurations and different clock frequencies. System performance is further improved by integrating the memory controller on a single die with the central processing unit which improves the speed of transactions between the CPU and memory controller.


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