Programmable memory access parameters

Details Programmable memory access parameters Programmable memory access parameters

2007-06-26

2007-06-26

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S189050

Reexamination Certificate

active

11187356

ABSTRACT:
A programmable device can configure memory access parameters to optimize the performance of one or more of its memory units. A memory unit includes one or more programmable delay units connected with clock, control and/or data signals. The configuration data of the programmable device specifies delay values for each programmable delay unit. A programmable delay unit includes at least two signal paths having different timing characteristics. A switching circuit controlled by configuration data is used to select one of the signal paths as the output of the programmable delay unit. Programmable delay units can be connected in series or in parallel to increase the number of possible delays and/or to specify timing parameters of portions of the memory unit in absolute or relative terms. Programmable delay units can be used to vary the timing characteristics of the memory unit and to control the voltage split used to read data.

REFERENCES:
patent: 6735129 (2004-05-01), Akasaki et al.

Affiliated with

Also associated with

Rating

Programmable memory access parameters does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable memory access parameters, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable memory access parameters will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3810215