Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
Reexamination Certificate
2003-12-31
2008-10-28
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Transmission facility testing
C714S715000, C714S025000, C714S030000, C714S032000, C714S036000, C714S043000, C714S044000, C714S048000, C714S728000, C714S712000, C714S713000, C714S717000, C714S724000, C714S733000, C714S734000, C714S736000, C714S739000, C714S738000, C702S108000, C375S221000, C375S224000
Reexamination Certificate
active
07444558
ABSTRACT:
A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the link. A start bit in a register of the IC device is programmed, to request that the link be placed in a measurement mode. In this mode, the IC device instructs the other IC device to enter a loopback mode for the link. The IC device transmits a sequence of test symbols over the link and evaluates a loopback version of the sequence for errors. The sequence of test symbols have a data pattern, and are transmitted, as configured by the registers. Other embodiments are also described and claimed.
REFERENCES:
patent: 5228042 (1993-07-01), Gauthier et al.
patent: 5956370 (1999-09-01), Ducaroir et al.
patent: 5970073 (1999-10-01), Masuda et al.
patent: 6009488 (1999-12-01), Kavipurapu
patent: 6128750 (2000-10-01), Espy et al.
patent: 6690488 (2004-02-01), Reuman
patent: 6977960 (2005-12-01), Takinosawa
patent: 7127648 (2006-10-01), Jiang et al.
patent: 7191371 (2007-03-01), Hsu et al.
patent: 7257725 (2007-08-01), Osaka et al.
patent: 2004/0117707 (2004-06-01), Ellis et al.
patent: 2004/0117708 (2004-06-01), Ellis et al.
patent: 2004/0136319 (2004-07-01), Becker et al.
patent: 2004/0158675 (2004-08-01), Hirose
patent: 2004/0186688 (2004-09-01), Nejedlo
patent: 2004/0193986 (2004-09-01), Canagasaby et al.
patent: 2004/0204912 (2004-10-01), Nejedlo et al.
patent: 2004/0221056 (2004-11-01), Kobayashi
PCI—SIG, “PCI Express Base Specification Revision 1.0”, Apr. 2002, pp. 31,32,45,150-152,158-160, 164-169,181,182,197,222,231,241-243,378.
Ravi Budruk, et al. “PCI Express System Architecture”, PC System Architecture Series, MindShare, Inc., Sep. 2003 (Contents, pp. vii-xxxvii; and Chapter 14—Link Initialization & Training , pp. 499-553).
PCT International Search Report (dated May 9, 2005), International Application No. PCT/US2004/043427—International Filing Date Dec. 23, 2004 (11 pgs.).
Jay J. Nejedlo, “IBIST™ (Interconnect Built-in-Self-Test) Architecture and Methodology for PCI Express”, Institute of Electrical and Electronics Engineers, Proceedings International Test Conference 2003, Charlotte, NC, USA Sep. 30-Oct. 2, 2003 (IEEE, US vol. 2, Sep. 30, 2003) XP010685400, ISBN:0-7803-8106-8 (pp. 114-122).
Jay J. Nejedlo, “Tribute™ Board and Platform Test Methodology”, Institute of Electrical and Electronics Engineers, Proceedings International Test Conference 2003, Charlotte, NC, USA Sep. 30-Oct. 2, 2003 (IEEE, US vol. 2, Sep. 30, 2003) XP010685399, ISBN: 0-7803-8106-8 (pp. 106-113).
Blodgett Cass A.
Martwick Andrew W.
Mitbander Suneel G.
Renaud Lyonel
Schoenborn Theodore Z.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Trimmings John P
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