Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2009-04-01
2011-12-27
Sorrell, Eron J (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S008000, C710S010000, C326S062000
Reexamination Certificate
active
08086762
ABSTRACT:
A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.
REFERENCES:
patent: 4627070 (1986-12-01), Champlin et al.
patent: 4833605 (1989-05-01), Terada et al.
patent: 4833695 (1989-05-01), Greub
patent: 4967201 (1990-10-01), Rich, III
patent: 5329520 (1994-07-01), Richardson
patent: 5510950 (1996-04-01), Bills et al.
patent: 5594908 (1997-01-01), Hyatt
patent: 5617547 (1997-04-01), Feeney et al.
patent: 5660568 (1997-08-01), Moshayedi
patent: 5666071 (1997-09-01), Hawkins et al.
patent: 5726991 (1998-03-01), Chen et al.
patent: 5793990 (1998-08-01), Jirgal et al.
patent: 5803757 (1998-09-01), Wang
patent: 5933021 (1999-08-01), Mohd
patent: 5954811 (1999-09-01), Garde
patent: 5999021 (1999-12-01), Jang
patent: 6081570 (2000-06-01), Ghuman et al.
patent: 6087851 (2000-07-01), Kim et al.
patent: 6137734 (2000-10-01), Schoner et al.
patent: 6140956 (2000-10-01), Hillman et al.
patent: 6167026 (2000-12-01), Brewer et al.
patent: 6172524 (2001-01-01), Cho
patent: 6175556 (2001-01-01), Allen et al.
patent: 6183307 (2001-02-01), Laity et al.
patent: 6215412 (2001-04-01), Franaszek et al.
patent: 6259693 (2001-07-01), Ganmukhi et al.
patent: 6317804 (2001-11-01), Levy et al.
patent: 6346827 (2002-02-01), Yeung et al.
patent: 6434157 (2002-08-01), Dube′ et al.
patent: 6438717 (2002-08-01), Butler et al.
patent: 6483849 (2002-11-01), Bray et al.
patent: 6496880 (2002-12-01), Ma et al.
patent: 6516352 (2003-02-01), Booth et al.
patent: 6577157 (2003-06-01), Cheung et al.
patent: 6760781 (2004-07-01), Wang et al.
patent: 6789144 (2004-09-01), Lai et al.
patent: 6859825 (2005-02-01), Williams
patent: 6880078 (2005-04-01), Rabinovich
patent: 6895528 (2005-05-01), Cantwell et al.
patent: 7032139 (2006-04-01), Iryami et al.
patent: 7035228 (2006-04-01), Baumer
patent: 7080162 (2006-07-01), Conley et al.
patent: 7133416 (2006-11-01), Chamdani et al.
patent: 7221652 (2007-05-01), Singh et al.
patent: 7355987 (2008-04-01), Baumer
patent: 7373561 (2008-05-01), Baumer et al.
patent: 2001/0000161 (2001-04-01), Laity
patent: 2001/0009553 (2001-07-01), Homann
patent: 2001/0012288 (2001-08-01), Yu
patent: 2001/0015664 (2001-08-01), Taniguchi
patent: 2001/0017595 (2001-08-01), Cliff et al.
patent: 2001/0021953 (2001-09-01), Nakashima
patent: 2001/0043603 (2001-11-01), Yu
patent: 2002/0019173 (2002-02-01), Oliphant et al.
patent: 2002/0054569 (2002-05-01), Morkawa
patent: 2002/0095649 (2002-07-01), Sample et al.
patent: 2002/0157030 (2002-10-01), Barker et al.
patent: 2002/0163924 (2002-11-01), Kim
patent: 2002/0165924 (2002-11-01), Kim et al.
patent: 2003/0009307 (2003-01-01), Mejia et al.
patent: 2003/0048781 (2003-03-01), Pierson
patent: 2003/0120791 (2003-06-01), Weber et al.
patent: 2003/0172332 (2003-09-01), Rearick et al.
patent: 2003/0214974 (2003-11-01), Beverly et al.
patent: 2004/0068593 (2004-04-01), Helenic et al.
patent: 2004/0083077 (2004-04-01), Baumer et al.
patent: 2004/0088443 (2004-05-01), Tran et al.
patent: 2004/0117698 (2004-06-01), Tran et al.
patent: 2004/0141497 (2004-07-01), Amirichimeh et al.
patent: 2004/0141531 (2004-07-01), Amirichimeh et al.
patent: 2005/0190690 (2005-09-01), Tran
patent: 2006/0250985 (2006-11-01), Baumer
McKenzie, Alan, “Multi-Function Input/Output Pad Interfaces Shared Between Programmable and Microprocessor Cores, Integrated Within a Programmable SOC Solution,” Mar. 11, 2001, IP.com, pp. 1-4.
Cases et al., “Multiple Mode Selector for Input/Output Circuitry,” Jul. 1, 1994, IP.com, pp. 1-3.
International Search Report Issued Dec. 14, 2004 for International Application No. PCT/US03/34234, 5 pages.
Alaska Quad-Port Gigabit Ethernet Over Copper Transceivers, from http://www.marvell.com/products/transceivers/quadport/...., 1 page, printed May 8, 2007.
Alaska X10 Gigabit Ethernet Alaska Gigabit Ethernet Fast Ethernet Physical Layer (PHY) Transceiver Families Provide a Full Range of Ethernet Transceiver Solutions for the Broadband Communications Industry, from http://www.nuhorizons.com/FeaturedProducts/Volume3/Marvell/phy—transceiver.asp, 4 pages, Copyright 2007, printed May 8, 2007.
Cisco Search: Results for “cdl” within “News@Cisco”, from http://www.cisco.com/pcgi-bin/search/search.pl, Copyright 1992-2003, printed Jul. 29, 2003.
Industry Breakthrough: Marvell Announces the First Quad-Port Transceiver to Support Both Copper and Fiber-Optic Gigabit Ethernet Interfaces, from Business Wire at www.encyclopedia.com/printable/aspx?id=1G1:68912211, 4 pages, Jan. 9, 2001, printed May 8, 2007.
David Maliniak (ed.), Bel's integrated connector modules support Marvell's Alaska quad Gigabit Ethernet transceiver, from http://www.electronicsweb.com/Content
ews/...., 1 page, Dec. 14, 2000, printed May 8, 2007.
Marvell Gets Small, from http://www.lightreading.com/document.asp?doc—id=12004&print=true, 1 page, Feb. 19, 2002, printed May 8, 2007.
Marvell Introduces the Industry's Smallest Quad-Port Gigabit Transceiver Device, Enabling Ultra High Port Density Enterprise Switching Systems, from http://www.marvell.com/press/pressNewsDisplay.do?releaseID-41, 3 pages, Feb. 19, 2002, printed May 8, 2007.
Ed Turner, David Law, Sep. 17-19, 2001, “IEEE P802.3ae MDC/MDIO”, http://www.Ieee802.org/3/efm/public/sep01/turner.sub.-- 1.sub.--0901.pdf.
Q&A: Hiroshi Suzuki on Extending Ethernet Beyond the LAN, from http:/
ewsroom.cisco.com/dlls/innovators/optical/hiroshi—suzuki—qa.html, 3 pages, Copyright 1992-2003, printed Jul. 29, 2003.
IEEE Std. 802.3, Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and physical layer specifications, Section Two, pp. 9-55, Copyright 2002.
IEEE Std. 802.3, Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and physical layer specifications, Section Four, pp. 9-152, Copyright 2005.
Cisco Systems, Hiroshi Suzuki: Taking Ethernet Beyond the LAN, http:/
ewsroom.cisco.com/dlls/innovators/optical/hiroshi—suzuki—profile.html.
Cisco Systems, Q&A: Hiroshi Suzuki on Extending Ethernet Beyond the LAN, http:/
ewsroom.cisco.com/dlls/innovators/optical/hiroshi—suzuki—qa.html.
Cisco Systems, Innovators Profiles, http:/
ewsroom.cisco.com/dlls/innovators/inn—profiles.html.
Cisco Systems, Optical, http:/
ewsroom.cisco.com/dlls/innovatros/optical/.
Cisco Systems, Cisco Systems ad Aretae Interactive Launch Internet Powered Property (IP2), http:/
ewroom.cisco.com/dlls/global/asiapac
ews/2000/pr—07-25.html.
“Broadcom Announces thr First 0.13-micron CMOS Multi-Rate Gigabit Octal Serializers/Deserializers”[online], Broadcom Press Release, Oct. 29, 2002 [retrieved on Jul. 16, 2003]. Retrieved from the Internet: <URL: http://broadcom.com/cgi-bin/pr/prps.cgi?pr—id=PR021029> (5 pages).
“BCM8040 8-Channel Multi-rate 1.0-3.2-GBPS Retimer Switch” [online], Broadcom Products Site Guide [retrieved on Jul. 16, 2003]. Retrieved from the Internet: <URL: http://www.broadcom.com/products/8040.html> (2 pages).
“8-Channel Multi-Rate CMOS Retimer with Full Redundancy” [online], BCM8040 Product Brief, Broadcom Corporation
Baumer Howard A.
Tran Hoang T.
Broadcom Corporation
Sorrell Eron J
Sterne Kessler Goldstein & Fox P.L.L.C.
LandOfFree
Programmable management IO pads for an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable management IO pads for an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable management IO pads for an integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4293871