Programmable Logic with Pipelined Memory Operation

Details Programmable Logic with Pipelined Memory Operation Programmable Logic with Pipelined Memory Operation

2006-07-04

2006-07-04

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S093000, C326S041000, C365S189011, C365S189020

Reexamination Certificate

active

07071731

ABSTRACT:
Memory performance of an integrated circuit, such as a programmable logic integrated circuit, is increased by pipelining. In a single clock cycle, more than one operation may be performed on the memory, which improves bandwidth. In an implementation, the memory architecture having one port supports pipelining, so reading from and writing to the memory can be accomplished in a one clock cycle and both Read and Write operation can occupy the full clock cycle at the same time on the same port. The pipelining architecture has relatively minimal circuit changes compared to a standard memory architecture which not supporting simultaneous-clock-cycle reads and writes, without requiring two or more ports.

REFERENCES:
patent: 6600693 (2003-07-01), Kim
patent: 6870856 (2005-03-01), Schroth

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