Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-06-25
2001-05-22
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C327S067000
Reexamination Certificate
active
06236231
ABSTRACT:
BACKGROUND OF THE INVENTION
A standard that has recently been developed for signaling over short distances is known as low voltage differential signaling (“LVDS”). A description of LVDS can be found, for example, in “LVDS Owner's Manual; Design Guide”, National Semiconductor, Spring 1997. (The reference mentioned in the preceding sentence is hereby incorporated by reference herein in its entirety.) Although LVDS is limited to distances of a few meters, this constraint is not a problem for use of this type of signaling between devices (e.g., integrated circuits) on a printed circuit board or in other relatively compact systems.
Because programmable logic devices (“PLDs”) such as are shown in Cliff et al. U.S. Pat. No. 5,689,195 and Jefferson et al. U.S. patent application Ser. No. 09/266,235, filed Mar. 10, 1999 are often desired as components of systems of the type for which LVDS is suitable, it would be desirable to provide PLDs with LVDS capabilities. (The references mentioned in the preceding sentence are hereby incorporated by reference herein in their entireties.) In addition, improvements are constantly being sought for LVDS circuitry generally, in terms, for example, of more uniform speed performance throughout the permitted operating voltage range, improved rejection of spurious signals, protection against open or short-circuited inputs, etc.
In view of the foregoing it is an object of this invention to provide improved circuitry for LVDS generally.
It is another object of this invention to provide PLDs with LVDS capabilities.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of one aspect of the invention by providing PLDs with input/output (“I/O”) pins that are connected in parallel to several different kinds of input and/or output buffers, including LVDS input and/or output buffers. The PLD is programmable to allow any of the input and/or output buffers to which an I/O pin is connected to be used. This allows the PLD to provide LVDS capabilities, if that is what is desired, without having to dedicate I/O pins to that particular type of use. Because an LVDS connection requires a pair of I/O pins, while many other signaling protocols require only one I/O pin per connection, the PLD circuitry is programmable to allow I/O pins to be used in pairs for LVDS or individually for other types of signaling.
To help make the speed of LVDS circuitry more uniform across the operating voltage range permitted by the LVDS standard, circuitry is provided for strengthening at least one of complementary current sources or sinks used in LVDS input buffers when the operating voltage is such that the circuitry associated with the other current source or sink is no longer able to help the input buffer operate. The thus-strengthened current source or sink helps to maintain the speed of the input buffer even though the circuitry associated with the other current source or sink is no longer operating effectively. Hysteresis circuitry may be provided in LVDS input buffers to help the buffer reject spurious input signal fluctuations. Pull-up connections may be provided on LVDS input signal leads to help protect an LVDS input buffer from producing erroneous output signals in response to open or short-circuit conditions on those input signal leads.
An LVDS output buffer in accordance with the invention is constructed to help keep the output voltages within the LVDS standard or specification despite variations due to such factors as (1) manufacturing process inconsistencies, (2) temperature changes, and (3) power supply voltage fluctuations. The LVDS output buffer includes differential output switching circuitry connected in series via resistors between power and ground potentials. One of the resistor circuits preferably includes a current source which tends to increase in resistance as the power supply potential increases, thereby helping to counteract the effect of increasing power supply voltage. The transistors in the differential output switching circuitry and the resistors in series with that circuitry are made so that they all have similar changes in resistance due to manufacturing process variations and temperature changes. This helps keep the LVDS output voltages within LVDS specifications despite these types of variations or changes. Capacitors are also preferably included in the LVDS output buffer to improve the performance of the circuitry in relation to switching transients.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 5067007 (1991-11-01), Kanji et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5939904 (1999-08-01), Fetterman et al.
“LVDS Owner's Manual; Design Guide”, National Semiconductor Corporation, Spring 1997, Chapter 1, pp. 1-7.
“Block Diagram for NSM LVDS Output Buffer”, “Circuit Trace from National Semiconductor Device”, National Semiconductor Corporation.
ORCA Series 3 Field-Programmable Gate Arrays, Preliminary Data Sheet, Rev. 01, Lucent Technologies Inc., Microelectronics Group, Allentown, PA, Aug. 1998, pp. 1-80.
Optimized Reconfigurable Cell Array (ORCA), Or3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays, Preliminary Product Brief, Lucent Technolgies, Inc., Microelectronics Group, Allentown, PA, Nov. 1997, pp. 1-7 and unnumbered back cover.
“Using Phase Locked Loop (PLLs) in DL6035 Devices, Application Note”, Dyna Chip Corporation, Sunnyvale, CA, 1998, pp. i and 1-6.
“Using the Virtex Delay-Locked Loop, Application Note, XAPP132, Oct. 21, 1998 (Version 1.31)”, Xilinx Corporation, Oct. 21, 1998, pp. 1-14.
“Virtex 2.5V Field Programmable Gate Arrays, Advanced Product Specification, Oct. 20, 1998 (Version 1.0)”, Xilinx Corporation, Oct. 20, 1998, pp. 1-24.
DY6000 Family, FAST Field Programmable Gate Array, DY6000 Family Datasheet, Dyna Chip Corporation, Sunnyvale, CA, Dec. 1998, pp. 1-66.
Cliff Richard G.
Huang Joseph
Kim In Whan
Nguyen Khai
Sung Chiakang
Altera Corporation
Fish & Neave
Hoang Khue V.
Jackson Robert R.
Nelms David
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