Programmable logic integrated circuit architecture...

Details Programmable logic integrated circuit architecture... Programmable logic integrated circuit architecture...

2000-01-06

2001-08-14

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

06275065

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuits and their operation. More specifically, in one embodiment the invention provides an improved logic device, as well as an improved method of operating a logic device.
Logic devices and methods of their operation are well known to those of skill in the art. Programmable logic devices have found particularly wide application as a result of their combined low up-front cost and versatility to the user.
Altera's FLEX® and MAX® lines of programmable logic are among the most advanced and successful programmable logic devices. In the FLEX® 8000 logic devices, for example, a large matrix of logic elements (LEs) is utilized. In one commercial embodiment of such devices, each LE includes a 4-input look-up table for performance of combinational logic (e.g., AND, OR, NOT, XOR, NAND, NOR, and many others) and a register that provides sequential logic features.
The LEs are arranged in groups of, for example, eight to form larger logic array blocks (LABs). The LABs contain, among other things, a common interconnection structure. The various LABs are arranged in a two-dimensional array, with the various LABs connectable to each other and to pins of the device though continuous lines that run the entire length/width of the device. These lines are referred to as row interconnect (GH) and column interconnect (GV) or “global” interconnect lines. In Altera's line of production these may include what are referred to as “Horizontal FastTracks™” and “Vertical FastTracks™.”
The MAX® 7000 logic devices by way of contrast utilize what are commonly referred to as “macrocells” (analogous to LEs) as a basic logic element. The macrocells are arranged in groups of, for example, sixteen to form larger logic array blocks (LABs). A programmable interconnect array (PIA) selectively links together the multiple LABs. The PIA is a global bus that is fed by all dedicated inputs, I/O pins, and the various macrocells. The PIA is analogous to global interconnect, GHs and GVs. For example, the PIA may be fed by signals that will be used as logic inputs, global controls for secondary register functions in the LABs, input paths from I/O pins to registers that are used for setup of the device, etc.
Inputs to the LABs include inputs from pins (via I/O control blocks), the PIA, and various control (e.g. clock) pins. Logic inputs are provided to one or more of five AND devices, the outputs of which are provided to a product term select matrix. The product term select matrix selects which inputs will be provided to an OR or XOR function, or as secondary inputs to registers in the macrocell. Product terms may be shared between macrocells for complex logic functions. Outputs from the LABs are provided to the I/O control block to the PIA and/or various output pins.
The FLEX® and MAX® logic devices have met with substantial success and are considered pioneering in the area of programmable logic. While pioneering in the industry, certain limitations still remain. For example, the present invention recognizes that it would be desirable to further increase the flexibility of such devices to perform logic.
From the above it is seen that an improved programmable logic device and method of operation therefore is desired.
SUMMARY OF THE INVENTION
The present invention is a logic element or macrocell for a programmable logic device incorporating a lonely register feature so that combinatorial and registered functions may be implemented more efficiently in a single logic element. The logic element may also provide a shareable expander feature where logic modules and product terms in a particular LAB may be combined using a global interconnect with logic modules and product terms in other LABs within the programmable logic device. These features improve the overall utilization of the resources of the programmable logic device. Consequently, logic may be more densely packed in the PLD, and an individual PLD may be used to implement more complex functions and operations.
In particular, the logic element includes logic modules for implementing combinatorial logic and a register. The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer to an I/O pad of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may also be used as a shareable expander by programmably coupling the module through to a global interconnect and combining it with other logic modules in LABs coupled to the global interconnect. By using a logic module as a shareable expander, the logic module may still be used for other functionality at the same time. In particular, the logic module may have a regular logic module output and a shareable expander output.
In accordance with the teachings of this invention, a logic element for a programmable logic device is disclosed. The logic element includes a first multiplexer which is directly coupled through an output buffer to an I/O pad of the programmable logic device. A plurality of logic modules or product terms is coupled to the first multiplexer. The logic modules may be programmably configured to implement combinatorial logic functions. A register may be programmably coupled to the first multiplexer and the plurality of logic modules. The register allows the implementation of registered functions. A particular logic module may be programmably coupled to the register while other logic modules are programmably coupled to the first multiplexer, bypassing the register.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.


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