Programmable logic devices with two-phase latch circuitry

Details Programmable logic devices with two-phase latch circuitry Programmable logic devices with two-phase latch circuitry

2004-12-02

2008-03-18

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S019000, C326S095000, C326S096000, C326S097000

Reexamination Certificate

active

07346861

ABSTRACT:
Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least some others of the latches are enabled by the other phase of the clock signal. Accordingly, these latches collectively have two-phase operation. These two-phase latches may replace at least some single-phase, edge-triggered flip-flops in a user's logic design, and may thereby increase the speed at which the user's logic can be operated. Methods for converting a single-phase, edge-triggered flip-flop design to a logically equivalent design using at least some two-phase latches are disclosed.

REFERENCES:
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patent: 2003/0149943 (2003-08-01), Yoshikawa
patent: 2006/0015786 (2006-01-01), Mitra et al.
Ishii A. et al., “Optimizing two-phase, level-clocked circuitry”, Journal of the ACM (JACM), vol. 44, Issue 1, Jan. 1997, pp. 148-199.

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