Programmable logic devices with multi-standard byte...

Details Programmable logic devices with multi-standard byte... Programmable logic devices with multi-standard byte...

2005-11-08

2005-11-08

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S047000

Reexamination Certificate

active

06963223

ABSTRACT:
A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 6542096 (2003-04-01), Yap et al.
patent: 6650140 (2003-11-01), Lee et al.
patent: 6894530 (2005-05-01), Davidson et al.
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2005/0058186 (2005-03-01), Kryzak et al.
“ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC”, Preliminary Data Sheet, Jul. 2001, Agere Systems Inc., pp. 1-35.
“ORCA ORT8850 Field-Programmable System Chip (FPSC) Eight Channel x 850 Mbits/s Backplane Transceiver”, Product Brief, Jul. 2001, Agere Systems Inc., pp. 1-6.
“ORCA ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver”, Data Sheet, Aug. 2001, Agere Systems Inc., pp. 1-36.

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