Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-03-06
2001-07-03
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S041000
Reexamination Certificate
active
06255846
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices, and more particularly to circuitry for improving the multiplexing capabilities of programmable logic devices.
Programmable logic devices are well known as shown, for example, by Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Cliff et al. U.S. Pat. No. 5,963,049, Reddy et al. U.S. Pat. No. 5,977,793, and McClintock et al. U.S. Pat. No. 5,999,016, all of which are hereby incorporated by reference herein. Such devices typically include large numbers of relatively small logic modules, each of which is programmable to perform any of several relatively elementary logic functions on input signals applied to the logic module in order to produce one or more logic module output signals. A network of programmable interconnection conductors and other interconnection resources is provided on the device for conveying signals to, from, and/or between the logic modules so that very complex logic functions can be performed by concatenating multiple logic modules in various ways.
The circuitry of known programmable logic devices performs logic very well, and it can also perform some multiplexing operations. (By “multiplexing” is meant the dynamic selection of any one of two or more multiplexer input signals to be the multiplexer output signal. In other words, at different times during operation of the device, a different one of the multiplexer input signals can be selected to be the multiplexer output signal.) However, known programmable logic devices tend not to perform multiplexing especially efficiently. For example, known logic modules which include a four-input look-up table may only be able to perform a single two-to-one multiplexing operation. Two of the inputs to the look-up table are used as the multiplexer input signals, a third input to the look-up table is used as a multiplexer selection control signal, and the fourth input to the look-up table may be wasted. Not only is this relatively inefficient use of a logic module, but in addition large numbers of logic modules must be used to perform wide fan-in multiplexing, and these modules must be connected in series (at least to some extent), which inherently slows down multiplexing functions.
In view of the foregoing, it is an object of this invention to provide programmable logic devices with improved multiplexing capabilities.
It is a more particular object of this invention to improve the speed, efficiency, and economy with which programmable logic devices can perform multiplexing operations.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing logic module circuitry that includes a programmable four-input look-up table and that is augmented with additional circuitry for allowing the logic module to be alternatively used as a dynamic four-to-one multiplexer.
In a first type of embodiment the four inputs to the look-up table are also applied to the four inputs of a four-to-one multiplexer circuit, and the final output signal of the logic module is programmably selected from either the look-up table output or the multiplexer output. The four-to-one multiplexer may be controlled by control signals which are shared with other logic modules on the programmable logic device that includes the first-mentioned logic module.
In another type of embodiment preliminary selection circuitry is used to select from more than four input signals the signals that are to be applied to the four-input look-up table. This preliminary selection circuitry may be controlled by inputs to the look-up table which are not among the signals being selected by the preliminary selection circuitry.
Alternatively, this preliminary selection circuitry may be programmably controlled.
In still another type of embodiment four-to-one multiplexer circuitry is provided to select a multiplexer output signal from signals which have been either partly processed by the look-up table circuitry of the logic module or are raw inputs to the look-up table circuitry. The multiplexer circuitry is operated by additional inputs to the logic module.
As in the first-mentioned type of embodiment, various inputs to other types of logic modules in accordance with this invention can be shared by several logic modules on a programmable logic device. Such sharing by several logic modules is especially suitable for multiplexer selection control signals.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
REFERENCES:
patent: Re. 34363 (1993-08-01), Freeman
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4642487 (1987-02-01), Carter
patent: 4677318 (1987-06-01), Veenstra
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4774421 (1988-09-01), Hartmann et al.
patent: 4871930 (1989-10-01), Wong et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 5023606 (1991-06-01), Kaplinsky
patent: 5073729 (1991-12-01), Greene et al.
patent: 5121006 (1992-06-01), Pedersen
patent: 5122685 (1992-06-01), Chan et al.
patent: 5132571 (1992-07-01), McCollum et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5218240 (1993-06-01), Camarota et al.
patent: 5220214 (1993-06-01), Pedersen
patent: 5225719 (1993-07-01), Agrawal et al.
patent: 5255203 (1993-10-01), Agrawal et al.
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pederson et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5338984 (1994-08-01), Sutherland
patent: 5350954 (1994-09-01), Patel
patent: 5371422 (1994-12-01), Patel et al.
patent: 5414377 (1995-05-01), Freidin
patent: 5442306 (1995-08-01), Woo
patent: 5448186 (1995-09-01), Kawata
patent: 5455525 (1995-10-01), Ho et al.
patent: 5467029 (1995-11-01), Taffe et al.
patent: 5469003 (1995-11-01), Kean
patent: 5483178 (1996-01-01), Costello et al.
patent: 5509128 (1996-04-01), Chan
patent: 5600264 (1997-02-01), Duong et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5835998 (1998-11-01), Pedersen et al.
patent: 5905385 (1999-05-01), Sharpe-geisher
patent: 5909126 (1999-06-01), Cliff et al.
patent: 5963049 (1999-10-01), Cliff et al.
patent: 5977793 (1999-11-01), Reddy et al.
patent: 5999016 (1999-12-01), McClintock et al.
patent: 6020756 (2000-02-01), New
patent: 454352 A1 (1991-10-01), None
patent: 463746 A2 (1992-01-01), None
patent: 630115 A2 (1994-12-01), None
patent: 746105 A2 (1996-12-01), None
patent: 2300950 (1996-11-01), None
patent: 2311885 (1997-10-01), None
patent: WO 95/04404 (1995-02-01), None
patent: WO 95/22205 (1995-08-01), None
patent: WO 95/30952 (1995-11-01), None
R. C. Minnick, “A Survey of Microcellular Research,” Journal of the Association for Computing Machinery, vol. 14, No. 2, pp. 203-241, Apr. 1967.
S. E. Wahlstrom, “Programmable Logic Arrays—Cheaper by the Millions,” Electronics, Dec. 11, 1967, pp. 90-95.
Recent Developments in Switching Theory, A. Mukhopadhyay, ed., Academic Press, New York, 1971, chapters VI and IX, pp. 229-254, and 369-422.
The Programmable Gate Array Data Book,1988, Xilinx, Inc., San Jose, CA.
El Gamal et al., “An Architecture for Electrically Configurable Gate Arrays,” IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 394-398.
El-Ayat et al., “A CMOS Electrically Configurable Gate Array,” IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 752-762.
ACT Family Field Programmable Gate Array Databook,Apr. 1992, Actel Corporation, Sunnyvale, CA, pp. 1-35 through 1-44.
The Programmable Logic Data Book,1994, Xilinx, Inc., San Jose, CA, pp. 2-7, 2-12, and 2-13.
“XC5000 Logic Cell Array Family, Technical Data, Advance Information,” Xilinx, Inc., Feb. 1995.
Lane Christopher F.
Lee Andy L.
Pedersen Bruce B.
Altera Corporation
Fish & Neave
Jackson Robert R.
Sharifi Pejman
Tokar Michael
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