Programmable logic device with soft multiplier

Details Programmable logic device with soft multiplier Programmable logic device with soft multiplier

2005-05-03

2005-05-03

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C326S041000, C326S038000

Reexamination Certificate

active

06888372

ABSTRACT:
A programmable logic device is provided which includes a multi-port RAM block with a first port including first address registers and first data registers and with a second port including second address registers and a second data registers. At least one look-up table is stored in the RAM block. First programmable logic circuitry is programmed to operate as a shift register with multiple tap outputs to multiple first address registers. Second programmable logic circuitry is programmed to operate as accumulate circuitry which includes a multi-bit input coupled to multiple first data registers and includes an accumulator output.

REFERENCES:
patent: 5550782 (1996-08-01), Cliff et al.
patent: 6118720 (2000-09-01), Heile
patent: 6249143 (2001-06-01), Zaveri et al.
patent: 6255849 (2001-07-01), Mohan
Altera Technical Brief 5, “Implementing Multipliers in FLEX 10K EABs” Mar. 1996, 2 pages.
Altera, “Implementing FIR Filters in FLEX Devices” Feb. 1998, ver. 1.01, pp 1-24.
Altera, “Implementing Logic with the Embedded Array in FLEX 10K Devices” May 2001, ver. 2.1, pp 1-20.

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