Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2006-09-19
2006-09-19
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
07109753
ABSTRACT:
A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be programmably selectively chained, wherein each functional unit contains an operational block and output selection logic that are configured to programmably selectively implement any of a variety of operations (e.g., bitwise, logical, arithmetic, etc.) that may be performed on the outputs of single FSBs and/or several FSBs. In addition to the output routing channel, the PLD may also contain at least one input routing channel that is configured to facilitate the routing, registering, and/or selection of FSB input signals. In some cases, the FSB input routing channel may also include circuitry for performing elementary processing operations.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4871930 (1989-10-01), Wong et al.
patent: 4912345 (1990-03-01), Steele et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5128559 (1992-07-01), Steele
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5371422 (1994-12-01), Patel et al.
patent: 5483178 (1996-01-01), Costello et al.
patent: 5648732 (1997-07-01), Duncan
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5744980 (1998-04-01), McGowan et al.
patent: 5754459 (1998-05-01), Telikepalli
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5874834 (1999-02-01), New
patent: 5898602 (1999-04-01), Rothman et al.
patent: 5970254 (1999-10-01), Cooke et al.
patent: 5978260 (1999-11-01), Trimberger et al.
patent: 6006321 (1999-12-01), Abbott
patent: 6069487 (2000-05-01), Lane et al.
patent: 6084429 (2000-07-01), Trimberger
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6226735 (2001-05-01), Mirsky
patent: 6242947 (2001-06-01), Trimberger
patent: 6351142 (2002-02-01), Abbott
patent: 6362650 (2002-03-01), New et al.
patent: 6396303 (2002-05-01), Young
patent: 6407576 (2002-06-01), Ngai et al.
patent: 6453382 (2002-09-01), Heile
patent: 6467017 (2002-10-01), Ngai et al.
patent: 6531888 (2003-03-01), Abbott
patent: 6538470 (2003-03-01), Langhammer et al.
patent: 6556044 (2003-04-01), Langhammer et al.
patent: 6557092 (2003-04-01), Callen
patent: 6573749 (2003-06-01), New et al.
patent: 6591357 (2003-07-01), Mirsky
patent: 6628140 (2003-09-01), Langhammer et al.
patent: 6725441 (2004-04-01), Keller et al.
patent: 6731133 (2004-05-01), Feng et al.
patent: 6744278 (2004-06-01), Liu et al.
patent: 6774669 (2004-08-01), Liu et al.
patent: 6781410 (2004-08-01), Pani et al.
patent: 6788104 (2004-09-01), Singh et al.
patent: 6836839 (2004-12-01), Master et al.
patent: 6874079 (2005-03-01), Hogenauer
patent: 6924663 (2005-08-01), Masui et al.
patent: 2001/0029515 (2001-10-01), Mirsky
patent: 2002/0089348 (2002-07-01), Langhammer
patent: 2003/0088757 (2003-05-01), Lindner et al.
patent: 2004/0178818 (2004-09-01), Crotty et al.
patent: 2005/0166038 (2005-07-01), Wang et al.
patent: 0 461 798 (1991-12-01), None
patent: 2 283 602 (1995-05-01), None
Altera Corporation, “Implementing Multipliers in FLEX 10K EABs”, Technical Brief 5, Mar. 1996, pp 1-2.
Altera Corporation, “Implementing Logic with the Embedded Array in FLEX 10K Devices”, Product Information Bulletin 21, ver. 2.1, May 2001, pp. 1-20.
Analog Devices, Inc., The Applications Engineering Staff of Analog Devices, DSP Division,Digital Signal Processing Applications Using the ADSP-2100 Family(edited by Amy Mar), 1990, pp. 141-192, no mo.
Bursky, D., “Programmable Logic Challenges Traditional ASIC SoC Designs”,Electronic Design,Apr. 15, 2002, pp. 44, 46, 48.
Chhabra, A. et al., Texas Instruments Inc., “A Block Floating Point Implementation on the TMS320C54x DSP”, Application Report SPRA610, Dec. 1999, pp. 1-10.
QuickLogic Corporation, “The QuickDSP Design Guide”, Rev. B, Aug. 2001, pp. 1-38.
QuickLogic Corporation, “The QuickDSP Family Data Sheet”, Rev. B, Aug. 7, 2001, pp. 1-19.
Texas Instruments Inc., “TMS320C54x DSP Reference Set, vol. 1: CPU and Peripherals”, Literature No.: SPRU131F, Apr. 1999, pp. 2-1 through 2-16 and 4-1 through 4-29.
Xilinx Inc., “Xilinx Unveils New FPGA Architecture to Enable High-Performance, 10 Million System Gate Designs”, Xilinx Virtex-II Architecture Technology Backgrounder, Jun. 22, 2000, pp. 1-9.
Xilinx Inc., “Xilinx Announces DSP Algorithms, Tools and Features for Virtex-II Architecture”, Nov. 21, 2000, pp. 1-4.
Xilinx Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-2 (v1.3), Jan. 25, 2001, Module 2 of 4, pp. 1-50.
Xilinx Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-1 (v1.5), Apr, 2, 2001, Module 1 of 4, pp. 1-7.
Xilinx Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-2 (v1.5), Apr. 2, 2001, Module 2 of 4, pp. 1-36.
Xilinx Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-2 (v1.9), Nov. 29, 2001, Module 2 of 4, pp. 1-39.
Xilinx Inc., “Using Embedded Multipliers”, Virtex-II Platform FPGA Handbook, UG002 (v1.3), Dec. 3, 2001, pp. 251-257.
Altera Corporation
Chang Daniel
Fish & Neave IP Group of Ropes & Gray LLP
Ingerman Jeffrey H.
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