Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2002-04-24
2004-08-24
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
06781408
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices (PLDs), and, more particularly, to techniques for facilitating the use of function-specific blocks which may be included in such devices.
As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include “function-specific blocks” (FSBs) in addition to blocks of generic programmable logic resources. Typically, an FSB is a concentration of circuitry on a PLD that has been partly- or fully-hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. An FSB may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented as FSBs include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/ SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/ OR/NOR arrays, etc., or combinations thereof.
While the availability of FSBs on a PLD may lessen the need for programmably implementing such structures in soft-logic (e.g., by piecing together and configuring several blocks of generic programmable logic resources), the nature of the functions implemented in FSBs are often those which require inputs and/or outputs that are several bits wide (i.e., multi-bit signals). As a result, significant interconnection resources may be required simply for routing input and output signals to and from FSBs. The need for interconnection resources may be further compounded when FSB output signals undergo additional processing, such as bitwise/logical/mathematical operations, signal conditioning/manipulation, combination with output signals from other FSBs, and the like.
As a consequence, performance and usability bottlenecks may result from the inefficient allocation of interconnection resources for the purpose of routing signals to and from FSBs. Such performance bottlenecks may become acute in those PLD designs wherein the routing needs of the FSBs are accommodated primarily by diverting existing routing resources from the structures that surround the FSBs (e.g., blocks of generic programmable logic resources), such that the inefficient usage of those routing resources may sacrifice the usability of the neighboring structures.
SUMMARY OF THE INVENTION
The present invention relates to PLDs wherein dedicated output routing channels are provided to facilitate the processing of output signals generated by one or more FSBs while allowing general-purpose interconnection resources to be conserved.
A dedicated output routing channel that may be constructed in accordance with the principles of the present invention includes a plurality of selectively-chainable functional units that are programmably configurable to implement, in a relatively localized area, a variety of processing operations (e.g., bitwise/ logical/mathematical functions, combinations, etc.) that may be performed on the output signals generated by one or more FSBs.
In addition, dedicated input routing channels may also be provided to facilitate the routing, registering, and/or selection of the input signals supplied to the FSBs. In some cases, the dedicated input routing channels may also contain circuitry for performing elementary processing operations (e.g., various arithmetic, logical, and/or signal conditioning operations, etc.) on the signals to be supplied as inputs to the FSBs.
Further features of the invention, its nature, and various advantages, will be more apparent from the accompanying drawings and the following detailed description of the invention.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4871930 (1989-10-01), Wong et al.
patent: 4912345 (1990-03-01), Steele et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5128559 (1992-07-01), Steele
patent: 5371422 (1994-12-01), Patel et al.
patent: 5483178 (1996-01-01), Costello et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5744980 (1998-04-01), McGowan et al.
patent: 5754459 (1998-05-01), Telikepalli
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5874834 (1999-02-01), New
patent: 6069487 (2000-05-01), Lane et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6362650 (2002-03-01), New et al.
patent: 6407576 (2002-06-01), Ngai et al.
patent: 6453382 (2002-09-01), Heile
patent: 6467017 (2002-10-01), Ngai et al.
patent: 6538470 (2003-03-01), Langhammer et al.
patent: 6556044 (2003-04-01), Langhammer et al.
patent: 6628140 (2003-09-01), Langhammer et al.
patent: 0 461 798 (1991-12-01), None
patent: 2 283 602 (1995-05-01), None
“Implementing Multipliers in FLEX 10K EABs”, Technical Brief 5, Altera Corporation, Mar. 1996, pp. 1-2.
“Implementing Logic with the Embedded Array in FLEX 10K Devices”, Product Information Bulletin 21, ver. 2.1, Altera Corporation, May 2001, pp. 1-20.
“Xilinx Unveils New FPGA Architecture to Enable High-Performance, 10 Million System Gate Designs”, Xilinx Virtex-II Architecture Technology Backgrounder, Xilinx Inc., Jun. 22, 2000, pp. 1-9.
“Xilinx Announces DSP Algorithms, Tools and Features for Virtex-II Architecture”, Xilinx Inc., Nov. 21, 2000, pp. 1-4.
“Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-2 (v1.3), Xilinx Inc., Jan. 25, 2001, Module 2 of 4, pp. 1-50.
“Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-1 (v1.5), Xilinx Inc., Apr. 2, 2001, Module 1 of 4, pp. 1-7.
“Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-2 (v1.5), Xilinx Inc., Apr. 2, 2001, Module 2 of 4, pp. 1-36.
“Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-2 (v1.9), Xilinx Inc., Nov. 29, 2001, Module 2 of 4, pp. 1-39.
“Using Embedded Multipliers”, Virtex-II Platform FPGA Handbook, UG002 (v1.3), Xilinx Inc., Dec. 3, 2001, pp. 251-257.
A. Chhabra and R. Iyer, “A Block Floating Point Implementation on the TMS320C54x DSP”, Application Report SPRA610, Texas Instruments, Dec. 1999, pp. 1-10.
D. Bursky, “Programmable Logic Challenges Traditional ASIC SoC Designs”, Electronic Design, Apr. 15, 2002, pp. 44, 46, 48.
The Applications Engineering Staff of Analog Devices, DSP Division,Digital Signal Processing Applications Using the ADSP-2100 Family(edited by Amy Mar), Prentice-Hall, Inc., Englewood Cliffs, NJ, Copyright 1990 by Analog Devices, Inc., Norwood, MA, pp. 141-192.
“TMS320C54x DSP Reference Set, vol. 1: CPU and Peripherals”, Literature Number: SPRU131F, Texas Instruments, Apr. 1999, pp. 2-1 through 2-16 and 4-1 through 4-29.
“The QuickDSP Design Guide”, Rev. B, QuickLogic Corporation, Aug. 2001, pp. 1-38.
“The QuickDSP Family Data Sheet”, Rev. B, QuickLogic Corporation, Aug. 7, 2001, pp. 1-19.
Altera Corporation
Chang Daniel D.
Fish & Neave
Jackson Robert R.
LandOfFree
Programmable logic device with routing channels does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable logic device with routing channels, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device with routing channels will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3359501