Electronic digital logic circuitry – Reliability – Redundant
Patent
1994-02-22
1994-11-29
Hudspeth, David R.
Electronic digital logic circuitry
Reliability
Redundant
326 39, 326 44, H03K 19177
Patent
active
053693140
ABSTRACT:
A programmable logic device is provided that has redundant circuitry. When a portion of the programmable logic device circuitry is found to be defective, the redundant circuitry is switched into use in place of the defective circuitry by programming appropriate portions of the circuitry of the programmable logic device. The programmable logic device is arranged in rows and columns of programmable logic containing logic array blocks, which a user selectively configures by loading programming data into vertical and horizontal programming blocks. Programming blocks are used to program the logic array blocks and various associated logic circuitry. When the redundant circuitry is switched into place, the programming data is redirected to the appropriate programming blocks, so that the device functions identically, regardless of whether or not the redundant circuitry is used.
REFERENCES:
patent: Re33521 (1991-01-01), Mori et al.
patent: 3955261 (1976-11-01), Goldberg
patent: 4020469 (1977-04-01), Manning
patent: 4538247 (1985-08-01), Venkateswatan
patent: 4566102 (1986-01-01), Hefner
patent: 4691301 (1987-09-01), Anderson
patent: 4706216 (1987-11-01), Carter
patent: 4791319 (1988-12-01), Tagami et al.
patent: 4798976 (1989-01-01), Curtin et al.
patent: 4800302 (1989-01-01), Marum
patent: 4829198 (1989-05-01), Maley et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4928022 (1990-05-01), Marum
patent: 5019736 (1991-05-01), Furtek
patent: 5045720 (1991-09-01), Bae
patent: 5204836 (1993-04-01), Reed
Recent Developments in Switching Theory, A. Mukhopadhyay, ed., Academic Press, N.Y., 1971, chapters VI and IX, pp. 229-254 and 369-422.
K. Kokkonen et al., "Memories and Redundancy Techniques", Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 80-1, Feb., 1981.
J. Bindels et al., "Cost-effective Yield Improvement in Fault-tolerant VLSI Memory", Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 82-3, Feb., 1981.
S. Eaton et al., "A 100ns 64K Dynamic RAM using Redundancy Techniques", Digest of Technical Papers, IEEE International Solid-State Circuits Confernece, pp. 84-5, Feb., 1981.
F. Hatori et al., "Introducing Redundancy in Field Programmable Gate Arrays", Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, pp. 7.1.1-7.1.4, May, 1993.
Preliminary Data booklet for Altera 32 Macrocell High Density Max EPLD EPM5032, 1988, Altera Corporation, Santa Clara (now San Jose), Calif.
"Programmable Logic Devices with Spare Circuits for Use in Replacing Defective Circuits".
Patel Rakesh H.
Wong Myron W.
Altera Corporation
Hudspeth David R.
Jackson Robert R.
Treyz G. Victor
LandOfFree
Programmable logic device with redundant circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable logic device with redundant circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device with redundant circuitry will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-75759