Programmable logic device with multi-port memory

Details Programmable logic device with multi-port memory Programmable logic device with multi-port memory

1999-09-24

2001-04-17

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

C365S189050, C326S037000, C326S039000

Reexamination Certificate

active

06219284

ABSTRACT:

FIELD OF THE INVENTION
The field of the present invention is integrated circuits for implementing reconfigurable logic, such as field programmable gate arrays (“FPGAs”), that are specially designed for emulation systems. In particular, the present invention is directed to a FPGA having multiple blocks of multi-ported memory and a special port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state.
BACKGROUND OF THE INVENTION
Field programmable gate arrays such as those available from Xilinx, Altera, AT&T and others are widely used for implementing various types of logic functions. FPGAs offer an advantage over mask-programmed gate arrays and discrete logic because the logic functions carried out by an FPGA can be easily reprogrammed to meet the user's objectives.
FPGAs are traditionally structured in a multi-level hierarchy, with simple logic blocks capable of performing the desired logic functions combined together to form more complex blocks, which are then combined to form a complete chip. Designs intended for implementation in FPGAs often include memories. This is especially true in prototyping applications where the designs being prototyped of ten contain large and complex memories.
Some FPGAs provide a mechanism for implementing small amounts of memory. For example, the Xilinx 4000 series of FPGAs allow the user to implement thirty-two bits of random-access memory (“RAM”) for each configurable logic block (“CLB”). RAMs can also be constructed using the flip-flop storage elements in the CLBs. Combining these small RAMs into the larger memories found in real designs, however, is difficult, slow, and consumes much of the FPGA routing and logic resources. This problem is particularly severe when the memory to be implemented has multiple ports, especially multiple write ports which require even greater routing resources to satisfy the memory requirements. Routing of memory outputs additionally should not require a sizable expansion in the routing network. A further drawback of the existing devices is the lack of an easy way to observe the contents of the FPGA memories at a selected point in time or to initialize the memories to a predetermined state. The prior art has not effectively resolved these and other issues.
SUMMARY OF THE INVENTION
A first, separate aspect of the present invention is a memory for an integrated circuit for implementing reconfigurable logic where the memory allows flexible implementation of various types of large and multi-ported memories inside the integrated circuit.
A second, separate aspect of the present invention is a multi-ported memory for an integrated circuit for implementing reconfigurable logic.
A third, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic having a memory whose width and depth are configurable in a tradeoff fashion.
A fourth, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic, where the integrated circuit includes a multi-ported memory wherein the width and depth of each port may be configured independently of the width and depth of the other ports.
A fifth, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic and including a memory, where the memory includes a register that can read the contents of the memory synchronously such that the data read accurately represents a snapshot of the memory contents at a point in time.
A sixth, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic and including a memory, where the memory includes a register that can load data into the memory so that the memory is loaded to a predetermined state.
A seventh, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic, where the circuit includes a logic element, an interconnect network and a memory that uses the logic element to access the interconnect network, thereby alleviating the necessity of adding routing lines to the interconnect network just to satisfy the memory requirements.
An eighth, separate aspect of the present invention is an integrated circuit for implementing reconfigurable logic, where the circuit includes a logic element, an interconnect network and a memory that shares some but not all of the routing resources used by the logic element so that the logic element may still perform logic functions.


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