Programmable logic device with low power voltage level translato

Details Programmable logic device with low power voltage level translato Programmable logic device with low power voltage level translato

1994-10-17

1995-07-11

Westin, Edward P.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 37, 326 68, 327203, H03K 190185, H03K 190948

Patent

active

054324670

ABSTRACT:
A voltage translation circuit 6 and method of operating a circuit to provide voltage level translation, particularly for use in association with a programmable logic device 2. An input signal, is provided to an NMOS transistor N2 and a CMOS inverter 12. The inverter 12 drives an NMOS pulldown transistor N4. The drain of N2 is coupled to the input of an inverter 14, the output of which is also coupled to the translation circuit output. A source of PMOS pullup transistor P1 drives the input of inverter 14 to pullup the output to a high level.

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