Programmable logic device with hierarchical interconnection reso

Details Programmable logic device with hierarchical interconnection reso Programmable logic device with hierarchical interconnection reso

1997-05-13

1999-11-02

Tekar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, H01L 2500, H03K 19177

Patent

active

059777931

ABSTRACT:
A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4642487 (1987-02-01), Carter
patent: 4677318 (1987-06-01), Veenstra
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4774421 (1988-09-01), Hartmann et al.
patent: 4871930 (1989-10-01), Wong et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong e t al.
patent: 5023606 (1991-06-01), Kaplinsky
patent: 5073729 (1991-12-01), Greene et al.
patent: 5121006 (1992-06-01), Pedersen
patent: 5122685 (1992-06-01), Chan et al.
patent: 5132571 (1992-07-01), McCollum et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5218240 (1993-06-01), Camarota et al.
patent: 5220214 (1993-06-01), Pedersen
patent: 5225719 (1993-07-01), Agrawal et al.
patent: 5255203 (1993-10-01), Agrawal et al.
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5338984 (1994-08-01), Sutherland
patent: 5350954 (1994-09-01), Patel
patent: 5371422 (1994-12-01), Patel et al.
patent: 5448186 (1995-09-01), Kawata
patent: 5455525 (1995-10-01), Ho et al.
patent: 5457410 (1995-10-01), Ting
patent: 5467029 (1995-11-01), Taffe et al.
patent: 5469003 (1995-11-01), Kean
patent: 5483178 (1996-01-01), Costello et al.
patent: 5509128 (1996-04-01), Chan
patent: 5541530 (1996-07-01), Cliff et al.
R. C. Minnick, "A Survey of Microcellular Research," Journal of the Association for Computing Machinery vol. 14, No. 2, pp. 203-241, Apr. 1967.
S. E. Wahlstrom, "Programmable Logic Arrays--Cheaper by the Millions," Electronics, Dec. 11, 1967, pp. 90-95.
Recent Developments in Switching Theory, A. Mukhopadhyay, ed., Academic Press, New York, 1971, chapters VI and IX, pp. 229-254 and 269-422.
The Programmable Gate Array Data Book, 1988, Xilinx, Inc., San Jose, CA.
El Gamal et al., "An Architecture for Electrically Configurable Gate Arrays," IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 394-398.
El-Ayat et al., "A CMOS Electrically Configurable Gate Array," IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 752-762.
ACT Family Field Programmable Gate Array Databook, Apr. 1992, Actel Corporation, Sunnyvale, CA, pp. 1-35 through 1-44.
The Programmable Logic Data Book, 1994, Xilinx, Inc., San Jose, CA, pp. 2-7, 2-12, and 2-13.
"XC5000 Logic Cell Array Family, Technical Data, Advance Information," Xilinx, Inc., Feb. 1995.

Affiliated with

Also associated with

Rating

Programmable logic device with hierarchical interconnection reso does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic device with hierarchical interconnection reso, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device with hierarchical interconnection reso will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2140414