Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-05-19
2001-08-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000
Reexamination Certificate
active
06278288
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices, and more particularly to circuitry for improving the multiplexing capabilities of programmable logic devices.
Programmable logic devices are well known as shown, for example, by Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, filed Jun. 28, 1996, Cliff et al. U.S. Pat. No. 5,963,049, filed Feb. 28, 1997, Ruddy et al. U.S. Pat. No. 5,977,793, filed May 13, 1997, and McClintock et al. U.S. Pat. No. 5,999,016, filed Aug. 28, 1997, all of which are hereby incorporated by reference herein. Such devices typically include large numbers of relatively small logic modules, each of which is programmable to perform any of several relatively elementary logic functions on input signals applied to the logic module in order to produce one or more logic module output signals. A network of programmable interconnection conductors and other interconnection resources is provided on the device for conveying signals to, from, and/or between the logic modules so that very complex logic functions can be performed by concatenating multiple logic modules in various ways.
Logic modules (also sometimes called subregions) may be grouped together on a programmable logic device in a plurality of so-called regions of programmable logic. Regions may in turn be similarly grouped together on a programmable logic device in a plurality of so-called super-regions of programmable logic. Interconnection resources may be associated with each level in this hierarchy of subregions, regions, and super-regions, and additional interconnection resources may be provided for communicating between the hierarchical levels. For example, inter-subregion interconnection conductors may be provided for conveying signals between the subregions in each region. In addition, inter-region interconnection conductors may be provided for conveying signals between the regions in each super-region. And inter-super-region interconnection conductors may be provided for conveying signals between the super-regions.
The circuitry of known programmable logic devices performs logic very well, and it can also perform some multiplexing operations. (By “multiplexing” is meant the dynamic selection of any one of two or more multiplexer input signals to be the multiplexer output signal. In other words, at different times during operation of the device, different ones of the multiplexer input signals can be selected as the multiplexer output signal.) However, known programmable logic devices tend not to perform multiplexing especially efficiently. For example, known logic modules which include a four-input look-up table may only be able to perform a single two-to-one multiplexing operation. Two of the inputs to the look-up table are used as the multiplexer input signals, a third input to the look-up table is used as a multiplexer selection control signal, and the fourth input to the look-up table may be wasted. Not only is this relatively inefficient use of a logic module, but in addition large numbers of logic modules must be used to perform wide fan-in multiplexing, and these modules must be connected in series (at least to some extent), which inevitably slows down multiplexing operations. Also, the typical absence of dynamic multiplexing capability in the interconnection resources of programmable logic devices means that if multiplexing is desired at any level in a hierarchical structure, the signals to be multiplexed must first be applied to the logic module level where multiplexing can be done and then returned to the hierarchical level requiring the multiplexing (assuming that this hierarchical level is not the logic module level). This can necessitate substantial amounts of inter-level communication, which can be wasteful of resources on the device and which may again slow down multiplexing operations.
In view of the foregoing, it is an object of this invention to provide programmable logic devices with improved multiplexing capabilities.
It is a more particular object of this invention to provide programmable logic devices with multiplexing capabilities in the interconnection resources of those devices.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing circuitry for making connections between interconnection conductors on a programmable logic device, which connector circuitry can be dynamically controlled by time-varying data or control signals on the device to connect any of a plurality of signal sources to an output interconnection conductor. Typically, the above-mentioned signal sources include at least one interconnection conductor, and more than one interconnection conductor may be included among those sources. The signal sources may additionally include a logic module output signal. The signals for controlling the multiplexer or connector circuitry of the invention can come from other interconnection conductors on the device, from logic modules on the device, or from any other suitable sources on the device. Programmable logic connectors (“PLCs”) may be provided on the device for allowing programmable selection of the control signal from any of several sources. These sources may also include sources of fixed logic 1 or fixed logic 0 signals so that the connector circuitry may be alternatively controlled in a fixed rather than dynamic manner. The output signal of the connector circuitry of this invention may first pass through a driver before being applied to the destination interconnection conductor. In this way the connector circuitry additionally facilitates effective sharing of drivers by several possible signal sources. The connector circuitry of this invention may be included at any level or levels, or between any levels, in a hierarchical interconnection structure. Within any level of interconnection circuitry it may be particularly advantageous to include the connector circuitry of this invention where signals may transition from one type of interconnection conductor to another (e.g., from so-called horizontal interconnection conductors (associated with rows of logic regions) to so-called vertical interconnection conductors (associated with columns of logic regions)).
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
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Altaf Kurosu R.
Cliff Richard G.
Jefferson David
Lee Andy L.
McClintock Cameron
Altera Corporation
Fish & Neave
Jackson Robert R.
Sharifi Pejman
Tokar Michael
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