Programmable logic device with delay-locked loop

Details Programmable logic device with delay-locked loop Programmable logic device with delay-locked loop

1999-07-29

2001-02-20

Phan, Trong (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000

Reexamination Certificate

active

06191613

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to programmable logic devices, and in particular to start-up sequencers for programmable logic devices.
BACKGROUND
Programmable logic devices (PLDS) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs are becoming ever more popular, largely because they are less expensive in relatively small quantities and require less time to implement than semi-custom and custom integrated circuits.
FIG. 1
is a block diagram of one type of PLD, a field-programmable gate array (FPGA)
100
. FPGA
100
includes an array of configurable logic blocks (CLBs)
110
that are programmably interconnected to each other and to programmable input/output blocks (IOBs)
120
. The interconnections are provided by a complex interconnect matrix represented as horizontal and vertical interconnect lines
130
and
140
. This collection of configurable elements and interconnect may be customized by loading configuration data into internal configuration memory cells (not shown) that define how the CLBs, interconnect lines, and IOBs are configured. The configuration data may be read from memory (e.g., an external PROM) or written into FPGA
100
from an external device. The collective program states of the individual memory cells then determine the function of FPGA
100
.
CLBs
110
and IOBs
120
additionally include user-accessible memory elements (not shown), the contents of which can be modified as FPGA
100
operates as a logic circuit. These user-accessible memory elements, or “user logic,” include block RAM, latches, and flip-flops. The data stored in user logic is alternatively referred to as “user data” or “state data.”
The power of FPGA
100
is that its logical function can be changed at will. Such changes are accomplished by loading the configuration memory cells and resetting (or presetting) the user logic. A sequencer (not shown) controls the configuration process and is designed to prevent interconnect contention during configuration.
Modern FPGAs are complex integrated circuits. As integration levels and system complexity increases, the distribution of the system clock becomes more critical, and consequently more difficult. Clock distribution must take into account distribution topography across the circuit, propagation delays in routing the clock signal to all elements on the circuit, desired set-up and hold times, and variation in system design parameters.
Some conventional programmable logic devices address some of the problems of clock distribution by including a delay-locked loop (DLL) on chip. DLLs employ a controlled delay element to null clock distribution delays within the FPGA by comparing the phase of a reference clock signal with that of a feedback signal. The phase difference between the two signals is used to bring the signals into a fixed phase relation. DLLs typically output a “lock” signal once the signals are in a fixed phase relation. The lock signal is necessary to prevent timing errors that might occur in the absence of a stable clock.
Lucent Technologies, Inc., manufactures FPGAs, under the trademark Orca®, that include programmable clock managers (PCMs) capable of functioning as DLLS. A lock signal from the PCM indicates a stable clock in the FPGA. Unfortunately, the lock signal can pulse low before the output clock stabilizes, thereby falsely indicating a stable clock. Lucent thus suggests that the user integrate the lock signal over a time period suitable to the subject application. In other words, this conventional DLL configuration places the onus on the user to ensure that the output of the DLL is stable before relying upon the programmable logic device.
SUMMARY
The present invention is directed to a programmable logic device (PLD) that minimizes the risk of error due to an unstable clock signal. One PLD in accordance with the invention, a field-programmable gate array (FPGA), includes an integrated delay-locked loop that produces a lock signal internal to the FPGA. The FPGA also includes a sequencer and related global signals adapted to configure the FPGA using external data. During the configuration process, the sequencer disables the FPGA until receipt of the lock signal. The configuration process, including the establishment of a valid internal clock, is controlled entirely within the FPGA. Thus, the user is not required to monitor the status of the delay-locked loop.
In one embodiment, an FPGA in accordance with the invention can be fully or partially reconfigured without powering down the device. The delay-locked loop maintains a lock on the clock signal so that the sequencer need not wait for the lock signal after reconfiguration.


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Xilinx, Inc., “XAPP 132: Using the Virtex Delay-Locked Loop,” Oct. 21, 1998. pp. 1-14.
Xilinx, Inc., “XCell:The Quarterly Journal for Programmable Logic Users,” First Quarter, 1999.

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