Programmable logic device with circuitry for observing...

Details Programmable logic device with circuitry for observing... Programmable logic device with circuitry for observing...

2000-06-29

2002-11-12

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C326S039000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06481000

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices. More particularly, this invention relates to observing logic signals at the outputs of various programmable logic circuits on programmable logic devices and preloading data into such programmable logic circuits.
Programmable logic devices are integrated circuits that may be programmed by a user to perform various logic functions. As programmable logic devices become more complex, it is becoming desirable to observe the logic signals on internal device nodes in order to determine whether a device is functioning properly. The ability to observe such logic signals (e.g., at the outputs of logic elements or other programmable logic circuits) reduces test costs by reducing test development time and test run time during manufacturing. The ability to observe these logic signals also helps to reduce the time needed to successfully debug a given design for a programmable logic device. Being able to preload data into certain programmable logic circuits also reduces test costs and helps to reduce the time needed to debug a design.
It is therefore an object of the present invention to provide arrangements for observing logic signals from various programmable logic circuits on a programmable logic device.
It is another object of the present invention to provide arrangements for preloading data into certain programmable logic circuits on a programmable logic device.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the present invention by providing programmable logic devices that contain circuitry for observing logic signals from programmable logic circuits during device testing. The programmable logic devices may also contain circuitry for preloading test signals into the programmable logic circuits.
The programmable logic circuits each contain programmable logic that may be configured using configuration signals applied from memory cells or other suitable control elements in which programming data has been stored. If desired, the programmable logic circuits may be programmable logic elements that contain combinatorial logic such as look-up table logic and that contain register logic. Programmable logic elements are typically arranged in at least one column or row, and on some programmable logic devices are arranged in arrays containing both columns and rows.
Programmable logic elements may be organized in groups of logic called logic array blocks. Each logic array block may be part of a larger logic region called a group of logic array blocks. Interconnection conductors of various lengths may be used to interconnect the logic in regions of different sizes.
One aspect of the invention involves using an array of addressable access transistors to observe logic signals. In an array of programmable logic elements, each programmable logic element may be provided with an associated access transistor at its combinatorial or registered output. Decoder logic may be used to turn on a given row of the access transistors. Turning on the access transistors allows signals from the logic elements to be passed to a test register.
If desired, additional logic may be used to select a given column of logic elements from which it is desired to observe logic signals. A snapshot may be taken of the logic element signals at a given point in time by freezing the clock applied to the logic elements. Sense lines may be used to route logic signals from the access transistors to the test register. Each logic element may be connected to a pair of sense lines by a pair of respective access transistors (e.g., one access transistor used to observe combinatorial signals and one access transistor used to observe registered signals).
Another aspect of the invention involves the use of registers on a programmable logic device that may be connected in a scan chain by switching circuits (i.e., multiplexers) when it is desired to observe logic element signals. The switching circuits have logic element inputs that receive signals from logic elements. The switching circuits also have scan chain inputs. The outputs of the switching circuits are connected to the registers. During normal operation, the switching circuits are configured to connect their logic element inputs to their outputs so that the logic signals from the logic elements are stored in the registers. During register observation, the switching circuits are configured to connect their scan chain inputs to their outputs so that the logic signals stored in the registers may be scanned out of the registers through the scan chain. The registers can also be initialized using the scan chain. Clock and clear control logic may be used to prevent data corruption during transitions between modes (i.e., during the transition between register initialization and normal operation and during the transition between normal operation and register observation).
Similar switching circuits may also be provided to observe memory block signals that are stored in the input and output registers of a programmable logic device memory block and to initialize those registers if desired. The programmable logic device may have rows and columns of groups of logic array blocks. Each group of logic array blocks may contain a plurality of logic array blocks, each of which contains a plurality of memory elements, and a memory block. The switching circuits associated with the logic elements and the memory block switching circuits may be connected to form a number of scan chains, each of which is associated with a separate row of the groups of logic array blocks. This allows the registers in each row to be initialized in parallel and for logic signals in each row to be observed in parallel.
Another aspect of the invention involves programmable logic device arrangements in which logic signals may be observed by making logic element registers part of first-in-first-out (FIFO) programming chains that are used on the device to program certain programmable logic circuits. The logic element registers may be incorporated into the FIFO chains by connecting the output of a memory cell in the chain to either the master latch input or slave latch input of the register.
The memory cells in the chain may be programmed with programming data to configure programmable logic within the programmable logic circuits to which the memory cells are connected. During normal operation of the programmable logic device, the logic element registers that are connected in the FIFO chain are used to register signals in the logic elements.
The programmable logic device may be operated in a programming mode (when programming data is placed in the memory cells), a user mode (when the device is operating normally) and a verify mode (when the device is being tested). The logic element registers each have a clock input. The programmable logic device is provided with clock control logic for controlling the clock signals applied to the clock input to ensure that there is no possibility of data corruption when entering the user mode from the programming mode or when leaving the user mode to enter the verify mode.
Another aspect of the invention involves arrangements for observing register signals on a programmable logic device using a chain of shadow memory cells. The shadow memory cells may be made part of a first-in-first-out chain of regular memory cells that are used to apply programming data to configure logic in various programmable logic circuits on the programmable logic device. The shadow memory cells are not directly connected to any programmable logic circuits for configuring the logic in those circuits. Shadow memory cells may be interspersed between respective regular memory cells in the first-in-first-out programming chain. If desired, the shadow memory cells may be arranged in a chain that contains only shadow memory cells. After the logic element register data that is to be observed has been loaded into the shadow memory cells in the chain, the data may be unloaded from the cha

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