Programmable logic device with circuit portions common to both c

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement

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307465, H03K 190175, G06F 738

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active

052821633

ABSTRACT:
In a programmable logic device having a memory circuit for storing circuit configuration data and a logic gate block for realizing a logic circuit desired by a user on the basis of the circuit configuration data written into the memory circuit, a switching circuit is provided for controlling at least a part of a circuit for writing the circuit configuration data into the memory circuit so as to be utilized as a part of the logic circuit desired by the user after the circuit configuration.

REFERENCES:
patent: 4745579 (1988-05-01), Mead et al.
patent: 4783606 (1988-11-01), Goetting
patent: 4831573 (1989-05-01), Norman
patent: 4835414 (1989-05-01), Freidin
patent: 4975601 (1990-12-01), Steele
1989 IEEE Int'l Symposium on Circuits and Systems May 8-11, 1989; pp. 921-926; Onodera et al. "Step by Step Placement Strategies for Building Block Layout"; p. 922, col. 1, line 14-col. 2, line 31.
IEEE Transactions on Computer-Aided Design; vol. 4, No. 1, Jan. 1985, pp. 12-22; Ueda et al.; "Champ: Chip Floor Plan for Hierarchical VLSI Layout Design"; p. 14, col. 1, line 8-p. 16, col. 1, line 23; FIG. 7.
Integration, The VLSI Journal; vol. 6, No. 2, Jul. 1988; Amsterdam NL; pp. 127-146; Hsu et al.; "Also: A System for Chip Floorplan Design"; p. 131, line 40-p. 132; FIG. 1.
IEEE Transactions on Circuits and Systems; vol. 26, No. 6, Jun. 1979; pp. 377-388; Quinn et al.; "A Force Directed Component Placement Procedure for Printed Circuit Boards"; p. 378, col. 1, line 37-p. 379, col. 2, line 14.
Hung-Cheng Hsieh et al., Third-Generation Architecture Boosts Speed And Density Of Field-Programmable Gate Arrays, 1990, 31.2.1-31.2.7.

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