Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-03-02
2002-03-19
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
Reexamination Certificate
active
06359468
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices in which long-carry-chain logic can be implemented. More particularly, this invention relates to programmable logic devices including circuitry for “predicting” a carry result to speed up the remainder of a logic operation.
Programmable logic devices (“PLDs”) typically include (1) many regions of programmable logic, and (2) programmable interconnection resources for selectively conveying signals to, from, and/or between those logic regions. Each logic region is programmable to perform any of several different, relatively simple logic functions. The interconnection resources are programmable to allow the logic regions to work together to perform much more complex logic functions than can be performed by any individual logic region. Examples of known PLDs are shown in U.S. Pat. No. 3,473,160, U.S. Pat. No. Re. 34,363, U.S. Pat. Nos. 5,689,195 and 5,909,126, and U.S. patent application Ser. No. 09/266,235, all of which are hereby incorporated by reference herein in their entireties.
It is known to provide, in addition to the standard interconnection network, a “carry” output from one logic region connected directly to a carry input of a neighboring logic region. This allows the second logic region to more quickly perform a logic function that depends on the carry output of the first logic region, because the direct carry connection allows the carry output to propagate more quickly to the second logic region than if it were routed on the general interconnection network.
The carry feature has several different uses. One use may be in arithmetic functions, such as addition where different logic regions are handling different bits of a multiple-bit addition problem. In such a case, except for the logic region handling the least significant bits, each logic region needs to know the value of the carry output from the logic region handling the bits of immediately lower significance. In some cases, many logic regions may be involved in a “long-carry-chain” calculation.
In a carry chain configuration, although the data for all logic regions may arrive substantially simultaneously, none of the regions can complete its operations until the carry arrives from the immediately preceding region. In a short carry chain, the delay involved in having each region wait for the preceding region is minimal. However, in a long carry chain, the cumulative delay at regions toward the end of the chain (e.g., the most significant bits in the arithmetic addition example) could be substantial.
It would be desirable to be able to provide a programmable logic device in which the values of carry signals could be predicted or determined in advance of completion of the operation forming the carry signal.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a programmable logic device in which the values of carry signals can be predicted or determined in advance of completion of the operation forming the carry signal.
In accordance with the present invention, there is provided a programmable logic device having a plurality of regions of programmable logic. Each region has a plurality of input terminals and at least one output terminal, and each region is programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal. An interconnection network is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions. The programmable logic device is programmable to configure a plurality of the regions to perform a logic function requiring provision of at least one carry signal from one of the regions to another of the regions. The regions are arranged in groups, and the device further includes additional logic dedicated to propagating the carry signal to other regions without regard to completion of logic operations in the region. The additional logic includes circuitry for propagating the carry signal from one of the groups of regions to another of the groups of regions. That circuitry includes a carry-out in one of the groups for outputting a carry signal from that one of the groups and a carry-in in another of the groups for inputting a carry signal to that other group. The carry-in and the carry-out are arranged adjacent one another.
In accordance with another aspect of the invention, there is provided a programmable logic device having a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal. An interconnection network is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions. The programmable logic device is programmable to configure a plurality of the regions to perform a logic function requiring provision of at least one carry signal from one of the regions to another of the regions. The device further comprises additional logic dedicated to propagating the carry signal to others of the regions without regard to completion of logic operations in the one region. The additional logic includes circuitry in the one region for calculating, separately from the logic function, the value for the carry signal to be input to the other regions as a function of a signal propagated into the first region.
In accordance with yet another embodiment of the invention, there is provided a programmable logic device comprising a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal. An interconnection network is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions. The programmable logic device is programmable to configure a plurality of the regions into a chain of at least three regions to perform a logic function requiring provision of a carry signal from each of the regions to a subsequent region in the chain. The additional logic comprises circuitry in each of the regions for (i) receiving a carry signal from a region immediately preceding an immediately preceding region in the chain, (ii) receiving at least one propagation signal from the immediately preceding region in the chain, (iii) receiving at least one propagation signal from within the region, and (iv) producing a carry signal as a function of (1) the carry signal from the region immediately preceding the immediately preceding region in the chain, (2) the at least one propagation signal from the immediately preceding region, and (3) the at least one propagation signal from within the region.
In a preferred embodiment, the invention is implemented in a programmable logic device of the type described in copending, commonly-assigned U.S. patent application Ser. No. 09/516,921, filed concurrently herewith, which is hereby incorporated by reference herein in its entirety, and in above-incorporated U.S. Pat. No. 5,689,195 and applications Ser. Nos. 60/122,788 and 60/142,513. In such a programmable logic device, logic is arranged in regions, which are then arranged in groups or blocks spanning, preferably, ten rows of logic regions. The interconnection network includes local conductors, global conductors, and conductors of intermediate lengths.
In the preferred embodiment, each logic region preferably has four data inputs and the additional logic in each logic region is an arrangement of multiplexers that allow the logic region
Huang Wei-Jen
Ngai Tony
Park James
Pedersen Bruce B.
Altera Corporation
Fish & Neave
Ingerman Jeffrey H.
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