Programmable logic device with buried registers selectively mult

Details Programmable logic device with buried registers selectively mult Programmable logic device with buried registers selectively mult

1986-05-30

1988-07-19

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307466, 364716, H03K 19177, H03K 19092

Patent

active

047587474

ABSTRACT:
A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clock buffer is provided so that registers within the register pair can be clocked singly when in a preload mode or together when in a logic or verification mode. When in the logic mode, either the output of a buried state register or an output register is observed at the I/O pin under the control of a product term generated by the logic array. When in the preload mode the register to be preloaded is selected by an externally provided preload select signal. In the verification mode, which typically follows a programming mode, individually selected product terms within the logic array can be observed by clocking them into the register pairs.

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patent: 4430584 (1984-02-01), Someshwar et al.
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patent: 4593390 (1986-06-01), Hildebrand et al.
patent: 4680487 (1987-07-01), Kobayashi
Wu, "Pin Sharing in a PLA Code", IBM T.D.B., vol. 20, No. 2, Jul. 1977, p. 672.
O'Hara, Jr., "PLA Multifunction Output Latches", IBM T.D.B., vol. 20, No. 12, May 1978, pp. 5205-5208.

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