Programmable logic device with adjustable length delay line

Details Programmable logic device with adjustable length delay line Programmable logic device with adjustable length delay line

2000-05-16

2001-11-13

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

06316958

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of integrated circuits, and more specifically to programmable logic devices having on-chip delay line structures.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a class of integrated circuits (ICs) that can be programmed by a user to emulate various logic functions. Logic designers typically use PLDs to implement control logic in electronic systems because they are relatively easy to program, and often can be reprogrammed to update the emulated logic function. This often makes the use of PLDs less costly in comparison to custom hardwired or “application specific” integrated circuits (ASICs).
One major class of PLDs includes a set of input pins, a programmable AND plane connected to the input pins, an OR plane connected to output terminals of the AND plane, and a set of output pins connected to output terminals of the OR plane. The AND plane includes a series of column conductors, a series of row conductors, and a matrix of programmable switches provided at each intersection of a column conductor and a row conductor. Input signals are applied through the input pins to the column conductors, which are selectively applied to the row conductors through the programmable switches. Each row conductor performs a logic AND or NAND function on all input signals transmitted to that row conductor through a programmed switch (note that input signals are not passed to the row conductor through non-programmed switches). Because of the logic AND (or NAND) function performed by each row conductor, the row conductors are typically referred to as product-term (P-term) elements, and are represented by logic AND gates. These P-term elements generate P-term signals that are transmitted to the OR plane. The OR plane may be programmable to selectively connect each P-term element to any available OR gate, in which case the PLD is called a programmable logic array (PLA). Alternatively, the OR plane may be fixed, such that each P-term element is connected to an associated OR gate, in which case the PLD is called a programmable array logic (PAL) device.
Early PLAs and PALs were well received by logic designers. However, as logic functions grew increasingly larger and more complex, logic designers were required to wire together two or more small PLAs/PALs to provide sufficient logic capacity. Although this process was tolerated during development and testing, it increased the cost and size of production units. This generated a demand for PLDs with increasingly larger logic capacity.
To meet the ever-increasing demand for greater capacity, PLDs with increasingly complex architectures have been developed. One popular complex PLD type, known as complex programmable logic devices (CPLDs), includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD is structured like the two-level PLAs/PALs, described above. In effect, these CPLDs incorporate several early PLAs/PALs and associated connection circuitry onto a single integrated circuit, thereby allowing a circuit designer to implement a complex logic function using a single IC.
FIG. 1
shows a simplified block diagram of a CPLD
100
that includes features common to the XC9500 CPLD family produced by Xilinx, Inc. of San Jose, Calif. Each CPLD
100
of the XC9500 CPLD family consists of input/output (I/O) pins
110
, I/O blocks (IOBs)
120
, an interconnect switch matrix
130
, and several function blocks (FBs)
200
(four shown). IOBs
120
provide buffering for device input and output signals that are applied to I/O pins
110
. All input signals from IOBs
120
enter switch matrix
130
on switch matrix input lines
125
, and selected output signals from FBs
200
are fed back into switch matrix
130
on macrocell output lines
231
. Each FB
200
receives fifty-four (54) input signals on FB input lines
135
from switch matrix
130
and produces ninety (90) P-term signals that are applied to any of eighteen (18) macrocells, each macrocell being programmable to provide a sum-of-products term using selected P-term signals. For each FB
200
, up to eighteen output signals are selectively transmitted on macrocell output lines
231
to directly drive I/O blocks
120
(along with optional corresponding output enable signals). In addition, each FB
200
selectively receives global set/reset signals and global clock signals on global set/reset lines
112
and global clock lines
113
, respectively. These global signals are utilized to selectively synchronize, for example, the clocking operations of flip flops located in FBs
200
.
FIG.
2
(A) shows a simplified block diagram of an FB
200
. Each FB
200
includes an AND array
210
, product term (P-term) allocator circuit
220
, and eighteen macrocells
230
(
1
) through
230
(
18
). AND-array
210
receives fifty-four (54) signals on input lines
135
from the switch matrix
130
(see FIG.
1
), and generates ninety (90) P-term signals that are routed to the macrocells
230
(
1
) through
230
(
18
) via P-term allocator circuit
220
. The P-term allocator circuit
220
includes eighteen portions
220
(
1
) through
220
(
18
) that are associated with macrocells
230
(
1
) through
230
(
18
) , respectively. P-term allocator circuit
220
selectively routes the P-term signals from AND-array
210
to selected macrocells
230
(
1
) through
230
(
18
) in the manner described below. Output signals transmitted from the macrocells
230
(
1
) through
230
(
18
) are then routed back to the switch matrix
130
on macrocell output lines
231
for use as input signals in other FBs
200
, or are routed to corresponding I/O pins
110
through the IOBs
120
along with optional corresponding output enable (OE) signals, which are transmitted on P-term OE lines
225
.
FIG.
2
(B) is a simplified schematic diagram showing macrocell
230
(
2
), which is representative of all eighteen macrocells of FB
200
, in additional detail. Macrocell
230
(
1
) includes OR gate
232
, an exclusive OR (XOR) gate
233
, P-term routing multiplexers (MUXes)
234
through
237
, a D-type flip flop
238
and a bypass MUX
239
. As discussed further below, macrocell
230
(
2
) receives up to five “direct” P-term elements
211
(
1
) through
211
(
5
) and up to eighty-five (
85
) “indirect” P-term elements (four shown) through P-term allocator portion
220
(
2
). Unlike the “indirect” P-term elements, the P-term signals transmitted from “direct” P-term elements
211
(
1
) through
211
(
5
) are selectively routed either as logic signals that are applied to OR gate
232
(i.e., to generate a sum-of-products term), or as control signals that are selectively utilized to control the operation of macrocell
230
(
2
). Alternatively, P-term elements
211
(
1
) through
211
(
5
) may be routed by P-term allocator portion
220
(
2
) to other macrocells of FB
200
. OR gate
232
generates a sum-of-products term in response to selected P-term signals received from P-term allocator portion
220
(
2
) in accordance with a user's logic function. The sum-of-products term generated by OR gate
232
is transmitted to an input terminal of XOR gate
233
, which is also connected to the output terminal of P-term control MUX
234
. MUX
234
is controlled by a configuration memory cell (not shown) to selectively pass a P-term invert (PTINV) control signal from P-term invert line
221
to exclusive OR (XOR) gate
233
, which then selectively inverts the sum-of products term generated by OR gate
232
. P-term routing MUXes
235
through
237
selectively pass either P-term control signals received from P-term allocator portion
220
(
2
) or global control signals to the control terminals of flip flop
238
. For example, MUX
235
is controlled to selectively pass either a P-term set (PTS) control signal from P-term set line
222
or a global set/reset signal from global set/reset line
112
to set terminal S of flip flop
238
. MUX
236
is controlled to selectively pass either a P-term clock

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