Programmable logic device using a two bit security scheme to pre

Details Programmable logic device using a two bit security scheme to pre Programmable logic device using a two bit security scheme to pre

1998-01-20

2000-06-13

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711103, 711152, 711170, 326 8, 713200, G06F 1214, H04L 900

Patent

active

060761490

ABSTRACT:
For a data processing device having a main memory comprised of a non-volatile memory and a CPU, memory protection and security are ensured for its programs and so forth. An auxiliary memory for storing security bit data is provided, for example, in an EPROM that comprises the main memory. Assuming that the result read by the CPU is "0" when a current flows between a drain and a source of a transistor in the EPROM, and "1" when the current does not flow, then the security bit data read from two transistors A and B are A=1 and B=1, which means they are set so that access to the main memory and a write to the auxiliary memory are prohibited. With A=0 and B=0, security is set, but a write to the auxiliary memory is permitted; with A=1 (0) and B=0 (1), security is reset.

REFERENCES:
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patent: 5293610 (1994-03-01), Schwarz
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patent: 5349249 (1994-09-01), Chiang et al.
patent: 5557743 (1996-09-01), Pombo et al.
patent: 5826007 (1998-10-01), Sakaki et al.

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