Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-07-08
2008-07-08
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11205528
ABSTRACT:
A method and apparatus for a CPLD-structured ASIC. Circuit blocks associated with a programmed portion of a CPLD are configured to preserve timing associated with instantiation of a circuit design in the programmed portion of the CPLD. The circuit blocks have predetermined placement information obtained from the CPLD, and the placement information is used to locate CPLD-structured ASIC cells associated with the circuit blocks.
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Bowers Brandon W
Chiang Jack
Webostad W. Eric
XILINX Inc.
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