Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2005-03-15
2005-03-15
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S047000, C375S376000
Reexamination Certificate
active
06867616
ABSTRACT:
In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.
REFERENCES:
patent: 3218876 (1965-11-01), Berger
patent: 4494021 (1985-01-01), Bell et al.
patent: 4633488 (1986-12-01), Shaw
patent: 4719593 (1988-01-01), Threewitt et al.
patent: 4868522 (1989-09-01), Popat et al.
patent: 4959646 (1990-09-01), Podkowa et al.
patent: 5072195 (1991-12-01), Graham et al.
patent: 5075575 (1991-12-01), Shizukuishi et al.
patent: 5079519 (1992-01-01), Ashby et al.
patent: 5133064 (1992-07-01), Hotta et al.
patent: 5204555 (1993-04-01), Graham et al.
patent: 5239213 (1993-08-01), Norman et al.
patent: 5349544 (1994-09-01), Wright et al.
patent: 5394116 (1995-02-01), Kasturia
patent: 5397943 (1995-03-01), West et al.
patent: 5418499 (1995-05-01), Nakao
patent: 5420544 (1995-05-01), Ishibashi
patent: 5424687 (1995-06-01), Fukuda
patent: 5448191 (1995-09-01), Meyer
patent: 5506878 (1996-04-01), Chiang
patent: 5542083 (1996-07-01), Hotta et al.
patent: 5581214 (1996-12-01), Iga
patent: 5629651 (1997-05-01), Mizuno
patent: 5642082 (1997-06-01), Jefferson
patent: 5646564 (1997-07-01), Erickson et al.
patent: 5656959 (1997-08-01), Chang et al.
patent: 5699020 (1997-12-01), Jefferson
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5744991 (1998-04-01), Jefferson et al.
patent: RE35797 (1998-05-01), Graham et al.
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5815016 (1998-09-01), Erickson
patent: 5847617 (1998-12-01), Reddy et al.
patent: 5889436 (1999-03-01), Yeung et al.
patent: 5900757 (1999-05-01), Affarwal et al.
patent: 5963069 (1999-10-01), Jefferson et al.
patent: 5970110 (1999-10-01), Li
patent: 5974105 (1999-10-01), Wang et al.
patent: 5987543 (1999-11-01), Smith
patent: 5999025 (1999-12-01), New
patent: 6014048 (2000-01-01), Talaga, Jr. et al.
patent: 6043677 (2000-03-01), Albu et al.
patent: 6069506 (2000-05-01), Miller, Jr. et al.
patent: 6069507 (2000-05-01), Shen et al.
patent: 6104222 (2000-08-01), Embree
patent: 6114915 (2000-09-01), Huang et al.
patent: 6141394 (2000-10-01), Linebarger et al.
patent: 6249189 (2001-06-01), Wu et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6278332 (2001-08-01), Nelson et al.
patent: 6320469 (2001-11-01), Friedberg et al.
patent: 6373278 (2002-04-01), Sung et al.
patent: 6388478 (2002-05-01), Mann
patent: 6483886 (2002-11-01), Sung et al.
patent: 0 266 065 (1987-09-01), None
patent: 0-416-930 (1991-03-01), None
patent: 0-778-517 (1997-06-01), None
patent: 1-137646 (1989-05-01), None
Advanced Micro Devices, Inc., “Am2971 Programmable Event Generator (PEG),” Publication No. 05280, Rev. C, Amendment/0, pp. 4-286-4-303 (Jul. 1986).
Advanced Micro Devices, Inc., “AmPAL*23S8 20-Pin IMOX PAL-Based Sequencer,” Publication No. 06207, Rev. B, Amendment/0, pp. 4-102-4-121 (Oct. 1986).
DynaChip Corp., “Application Note: Using Phase Locked Loops in DL6035 Devices” (1998).
DynaChip Corp., DY6000 Family Datasheet (Dec. 1998).
Ko, U., et al., “A 30-ps Jitter, 3.6 μs Locking, 3.3-Volt Digital PLL for CMOS Gate Arrays,”Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, Publication No. 0-7803-0826-3/93, pp. 23.31-23.3.4 (May 9-12, 1993).
LSI Logic Corp., 500K Technology Design Manual (Document DB04-000062-00, First Edition), pp. 8-1-8-33 (Dec. 1996).
Lucent Technologies, Inc., Optimized Reconfigurable Cell Array (ORCA®) OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays, Preliminary Product Brief, (Nov. 1997).
Lucent Technologies, Inc., ORCA® Series 3 Field-Programmable Gate Arrays, Preliminary Data Sheet, Rev. 01 (Aug. 1998).
Monolithic Memories, Inc., “Programmable Array Logic PAL20RA10-20 Advance Information,” pp. 5-95-5-102 (Jan. 1988).
National Semiconductor Corp.,LVDS Owner's Manual&Design Guide(Apr. 25, 1997).
Xilinx, Inc., Virtex 2.5V Field Programmable Gate Arrays Advance Product Specification (Version 1.0) (Oct. 20, 1998).
Xilinx, Inc., Application Note: Using the Virtex Delay-Locked Loop (Version 1.31) (Oct. 21, 1998).
Zaks, R., Et al.,From Chips to Systems: An Introdction to Microcomputers, pp. 54-61 (Prentice-Hall, Inc., Englewood Cliffs, N.J., 1987).
Lee Chong H.
Patel Rakesh
Venkata Ramanand
Altera Corporation
Chang Daniel D.
Fish & Neave IP Group of Ropes & Gray LLP
Ingerman Jeffrey H.
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