Programmable logic device routing architecture

Details Programmable logic device routing architecture Programmable logic device routing architecture

1994-01-06

1995-11-21

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 21, 326101, H03K 19177

Patent

active

054690781

ABSTRACT:
An integrated electronic circuit architecture has low leakage current and capacitance and includes a user-programmable integrated circuit design (110) having a plurality of designed conductors (112, 118) and a plurality of designed functional circuit blocks (e.g., 12,14, etc.). In the architecture, a plurality of user-programmable antifuse elements (e.g., 26, 28, 30, etc.) connect to the plurality of conductors (112, 118) and the plurality of functional circuit blocks (12, 14, 16, etc.). The plurality of user-programmable antifuse elements (e.g., 26, 28, 30, etc.) connect the plurality of conductors (112, 118) with one another and to the plurality of functional circuit blocks (12, 14, 16, etc.). The plurality of conductors (112, 118) is segregated into at least two groups including a first group of conductors and a second group of conductors. Antifuses (26, 28, 32) in the first group of conductors are selectively depopulated to reduce capacitance and leakage associated with their placement in the user-programmable integrated circuit (110), while the conductors of the first group of conductors permit access to conductors in the second group of conductors. Segmentation transistors (114, 122, 136) separate the first group of conductors from the second group of conductors.

REFERENCES:
patent: 4433331 (1984-02-01), Kollaritsch
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patent: 4758745 (1988-07-01), Elgamal et al.
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patent: 5073729 (1991-12-01), Greene et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5191241 (1993-03-01), McCollum et al.
patent: 5341040 (1994-08-01), Garverick et al.

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