Programmable logic device multispeed I/O circuitry

Details Programmable logic device multispeed I/O circuitry Programmable logic device multispeed I/O circuitry

2003-01-07

2004-12-14

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S037000, C326S039000, C326S041000

Reexamination Certificate

active

06831480

ABSTRACT:

BACKGROUND OF THE INVENTION
This application relates to programmable logic array integrated circuits (“programmable logic devices”), and more particularly, to input-output circuitry for programmable logic devices.
Programmable logic devices are integrated circuits that may be programmed by a user to perform various logic functions. Some currently-available programmable logic devices have I/O driver circuitry that can be selectively configured to accommodate different I/O signaling standards. This flexibility enhances the usefulness of such devices, because they may be used in various system environments and may communicate with a broader range of other devices than would otherwise be possible. However, substantial performance penalties may arise if the input-output circuitry of a programmable logic device is made too flexible.
On some currently-available programmable logic devices the transmitters (output drivers) in the I/O circuitry may be made more programmable than the receivers (input drivers) to take advantage of the less-sensitive nature of the transmitters to performance penalties when adding support for multiple-signaling standards. On these devices higher speed I/O circuits may be provided with less programmability to maximize their performance. Performance is enhanced further by reducing the amount of signal conductor area that immediately underlies the flip-chip solder bump pads at the ends of the I/O lines on the programmable logic device.
It is therefore an object of the present invention to provide programmable logic devices that have input-output circuitry with both flexibility and high performance.
SUMMARY OF THE INVENTION
This and other objects of the invention are accomplished in accordance with the principles of the invention by providing a programmable logic device having input-output driver circuitry that is at least partially divided into separate blocks or portions. With this approach, some or all of the highest-speed I/O circuitry may be segregated from the lowest speed I/O circuitry.
The performance penalty for providing flexible I/O driver circuits is relatively low when the I/O speeds involved are low and is relatively high when the I/O speeds are high. Accordingly, the lowest speed I/O circuitry may be provided with more flexibility than the highest speed I/O circuitry while still maintaining good I/O performance. If desired, the I/O circuitry may be subdivided into three or more different types of I/O driver circuits. For example, one I/O circuit type may be used to support high-speed differential signals and may be either not programmable or only slightly programmable. Another I/O circuit type may be used to support intermediate-speed signals (some differential and some not). Yet another I/O circuit type may be used to support low-speed signals.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.


REFERENCES:
patent: 3473160 (1969-10-01), Wahistrom
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 4527079 (1985-07-01), Thompson
patent: 4658156 (1987-04-01), Hashimoto
patent: 4853560 (1989-08-01), Iwamura et al.
patent: 5059835 (1991-10-01), Lauffer et al.
patent: 5067007 (1991-11-01), Otsuka et al.
patent: 5144167 (1992-09-01), McClintock
patent: 5268598 (1993-12-01), Pedersen et al.
patent: RE34808 (1994-12-01), Hsieh
patent: 5371422 (1994-12-01), Patel et al.
patent: 5521530 (1996-05-01), Yao et al.
patent: 5557219 (1996-09-01), Norwood et al.
patent: 5589783 (1996-12-01), McClure
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5742178 (1998-04-01), Jenkins, IV et al.
patent: 5764080 (1998-06-01), Huang et al.
patent: 5801548 (1998-09-01), Lee et al.
patent: 5936423 (1999-08-01), Sakuma et al.
patent: 5939904 (1999-08-01), Fetterman et al.
patent: 5958026 (1999-09-01), Goetting et al.
patent: 5970255 (1999-10-01), Tran et al.
patent: 5974476 (1999-10-01), Lin et al.
patent: 6175952 (2001-01-01), Patel et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6239612 (2001-05-01), Shiflet
patent: 6239615 (2001-05-01), Ngai et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6271679 (2001-08-01), McClintock et al.
patent: 6400598 (2002-06-01), Nguyen et al.
patent: 6407576 (2002-06-01), Ngai et al.
patent: 6433579 (2002-08-01), Wang et al.
patent: 6472903 (2002-10-01), Veenstra et al.
patent: 6480026 (2002-11-01), Andrews et al.
patent: 6590419 (2003-07-01), Betz et al.
patent: 6650141 (2003-11-01), Agrawal et al.
patent: 2002/0190751 (2002-12-01), Lee et al.
patent: 0 575 124 (1993-12-01), None
“A 3.3-V Programmable Logic Device that Addresses Low Power Supply and Interface Trends,” IEEE 1997 Custom Integrated Circuits Conference, May 1997, pp. 539-42. —Patel et al..
“APEX20KC programmable Logic Device Data Sheet”, Apr. 2002 ver. 2.1, pp. 1-8.
“APEX II Programmable Logic Device Family Data Sheet”, Apr. 2001 ver. 1.0, pp. 24-36.
“Block Diagram for NSM LVDS Output Buffer”, “Circuit Trace from National Semiconductor Device”, National Semiconductor Corporation. —No date provided.
“Lucent Introduces 10Gb/s Ethernet FPGAs”, Programmable Logic News and Views, Electronic Trend Publications, Inc., vol. IX, No. 11, Nov. 2000, pp. 7-8.
“LVDS Owner's Manual; Design Guide”, National Semiconductor Corporation, Spring 1997, Chapter 1, pp. 1-7.
Mercury Programmable Logic Device Family Data Sheet, Mar. 2002, ver. 2.0, pp. 1-60.
“ORCA ORT82G5 0.622/1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC”, Product Brief, Feb. 2001, Lucent Technologies Inc., pp. 1-8.
“Protocol Independent Gigabit Backplane Transceiver Using Lucent ORT4622/ORT8850 FPSCs”, Application Note, Jun. 2000, Lucent Technologies Inc., pp. 1-10.
“Using HSDI in Source-Synchronous Mode in Mercury Devices, Application Note 159”, Altera Corporation, Sep. 2001, ver. 1.0.
“Using Phase Locked Loop (PLLs) in DL6035 Devices, Application Note”, Dyna Chip Corporation, Sunnyvale, CA, 1998, pp. i and 1-6.
“Using the Virtex Delay-Locked Loop, Application Note, XAPP132, Oct. 21, 1998 (Version 1.31)”, Xilinx Corporation, Oct. 21, 1998, pp. 1-14.
“Virtex™—E 1.8V Field Programmable Gate Arrays Preliminary Product Specification”, Xilinx, DS022-2 (vs.3), Nov. 9, 2001, pp. 1-52.
“Virtex-II 1.5V Field-Programmable Gate Arrays Advance Product Specification”, Xilinx, DS031-2 (v2.0), Jul. 16, 2002.
“Virtex 2.5V Field Programmable Gate Arrays, Advanced Product Specification, Oct. 20, 1998 (Version 1.0)”, Xilinx Corporation, Oct. 20, 1998, pp. 1-24.
DY6000 Family, FAST Field Programmable Gate Array, DY6000 Family Datasheet, Dyna Chip Corporation, Sunnyvale, CA, Dec. 1998, pp. 1-66.
Optimized Reconfigurabl Cell Array (ORCA), OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays, Preliminary Product Brief, Lucent Technolgies Inc., Microelectronics Group, Allentown, PA, Nov. 1997, pp. 1-7 and unnumbered back cover.
ORCA Series 3 Field-Programmable Gate Arrays, Preliminary Data Sheet, Rev. 01, Lucent Technologies Inc., Microelectronics Group, Allentown, PA, Aug. 1998, pp. 1-80.
Rocket I/O Transceiver User Guide, UG024 (vl.2) Feb. 25, 2002, Xilinx, Inc., pp. 1-106.
Virtex-II Pro Platform FPGA Handbook, UG012 (vl.0) Jan. 31, 2002, Xilinx, Inc., pp. 1-6 27-32. 121-126, and 162-180.

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