Programmable logic device multi-boot state machine for...

Details Programmable logic device multi-boot state machine for... Programmable logic device multi-boot state machine for...

2007-08-07

2008-09-16

Cho, James H (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S047000

Reexamination Certificate

active

07425843

ABSTRACT:
Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.

REFERENCES:
patent: 7281082 (2007-10-01), Knapp
patent: 7301822 (2007-11-01), Walstrum et al.
U.S. Appl. No. 11/131,751, filed May 18, 2005; James A. Walstrum, Jr. et al., entitled “Multi-Boot Configuration of Programmable Devices”, Xilinx, Inc. 2100 Logic Drive, San Jose, CA, 36 pages.
U.S. Appl. No. 11/131,764, filed May 18, 2005; James A. Walstrum, Jr. et al., entitled “Parellel Interface for Configuring Programmable Devices”, Xilinx, Inc. 2100 Logic Drive, San Jose, CA, 36 pages.

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