Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
1998-06-30
2001-09-11
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C326S039000, C365S189080
Reexamination Certificate
active
06288970
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices. More particularly, this invention relates to programmable logic device memory arrays.
Programmable logic devices are integrated circuits that may be programmed by a user to perform various logic functions. At their most basic level, programmable logic devices contain programmable components, such as erasable programmable read-only memory (EPROM) transistors, electrically erasable programmable read-only memory (EEPROM) transistors, random access memory (RAM) transistors or cells, fuses, and antifuses. Higher-level functions are provided by organizing the programmable components into groups of components. The groups of components are electrically connected to one another by programmable interconnections. Illustrative programmable logic devices are described in Cliff et al. U.S. pat. No. 5,689,195.
Programmable logic devices such as those described in U.S. pat. No. 5,689,195 generally have arrays of random-access memory (RAM) for storing data during device operation. The memory arrays, which are sometimes referred to as embedded array blocks (EABs), are made up of rows and columns of memory cells. The word size used to access data in the memory arrays is generally smaller than the physical dimensions of the memory arrays. For example, a two kilobit (2K) memory array might have 64 rows and 32 columns of memory cells for storing data, whereas the device might use eightbit data words. When it is desired to read or write a data word, the eight data bits are either retrieved from or written to the memory array.
Memory arrays of this type may be provided with a variable depth and width feature that allows the size of the data word that is used to access the memory array (its “width”) and the resulting capacity of the array for data storage (its “depth”) to be selectively programmed by the user. A typical 2K variable depth and width memory array can be programmed to have the respective depth and width configurations of: 2K×1, 1K×2, 512×4, or 256×8. With such variable depth and width memory arrays, data may be either written to or read from the array in words of the selected width. However, data cannot be written to and read from such conventional arrays simultaneously. This capability is needed for applications in which the memory array is used to implement a first-in-first-out buffer or in other such applications in which the memory array is shared between two concurrent processes, one of which reads data from the array and one of which writes data to the array.
A dual-port programmable logic device memory array arrangement that allows data words to be written and read simultaneously is described in Reddy et al. patent application Ser. No. 09/107,533, filed Jun. 30, 1998. One such dualport memory array is typically associated with each of the rows of programmable logic regions on a programmable logic device. This arrangement allows the memory array to be used to implement first-in-first-out buffers and other such applications. However, sometimes all or part of a logic design does not need the dual-port capabilities of such memory arrays. Logic resources may be wasted when single-port memory arrays with smaller data width configurations would have sufficed.
It is therefore an object of the present invention to provide a programmable logic device memory array circuit containing a pair of single-port memory arrays that may either be operated individually or combined when a memory array with dual-port capabilities is desired.
SUMMARY OF THE INVENTION
This and other objects of the invention are accomplished in accordance with the principles of the present invention by providing a programmable logic device memory array circuit formed from a pair of combinable single-port memory arrays. A typical programmable logic device in which such a memory array circuit may be used has a number of regions of programmable logic organized in intersecting rows and columns. One of the programmable logic device memory array circuits may be associated with each row of such logic regions. The rows and columns of logic regions and memory array circuits may be interconnected with associated groups of horizontal and vertical interconnects. The combinable single-port memory arrays are preferably memory arrays having a userprogrammable depth and width.
The memory array circuit may be operated either as two individual single-port memory arrays or as a single dual-port memory array. When operated individually, data may be written to each single-port memory array or read from that single-port memory array, but data may not be written to and read from the memory array concurrently. When operated as a single dual-port memory array, data may be written to the array at the same time that data is being read from the array. This ability to handle concurrent reading and writing operations in dual-port mode allows the user to implement logic circuit designs with the memory array circuit that would otherwise not be possible. Because the combinable single-port memory arrays may be used individually, logic resources are not wasted when the dual-port function of the memory array circuit is not needed.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
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“XC
Lane Christopher F.
Mejia Manuel
Reddy Srinivas T.
Altera Corporation
Fish & Neave
Jackson Robert R.
Phan Trong
Treyz G. Victor
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