Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2001-05-01
2002-01-01
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C710S108000
Reexamination Certificate
active
06335636
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an input/output circuit for a programmable logic device, and more particularly to an input/output circuit that is configurable to be used either as a reference voltage input circuit to accommodate different logic standards with different voltage requirements, or as an ordinary input/output circuit.
Programmable logic devices are well known. Commonly, a programmable logic device has a plurality of substantially identical logic elements, each which can be programmed to perform certain desired logic functions. The logic elements have access to a programmable interconnect structure that allows a user to interconnect the various logic elements in almost any desired configuration. Finally, the interconnect structure also provides access to a plurality of input/output (“I/O”) pins, with the connections of the pins to the interconnect structure also being programmable.
At one time, programmable logic devices of the type just described were implemented almost exclusively using transistor-transistor logic (“TTL”), in which a logical “high” signal was nominally at 5 volts, while a logical “low” signal was nominally at ground potential, or 0 volts. More recently, however, other logic standards have come into general use, some of which use different signalling schemes, such as LVTTL (Low Voltage TTL, which exists in a 3.3-volt version or a 2.5-volt version), PCI (Peripheral Component Interface, which requires a 3.3-volt power supply), SSTL (Series Stub Terminated Logic, which has several variants), GTL (Gunning Transceiver Logic) or GTL+, HSTL (High Speed Transceiver Logic, which has several variants), LVDS (Low Voltage Differential Signalling), and others. Not only might these signalling schemes use different voltage levels for a “high” signal, and therefore require different supply voltages (the power supply requirements for these various standards may be 5.0 volts, 3.3 volts, 2.7 volts, 2.5 volts, 1.8 volts or 1.5 volts), but some of them, such as GTL/GTL+, various variants of SSTL and HSTL, and other standards such as CTT, ECL and 3.3V AGP, may require a source of reference voltage. Typically, reference voltage would be supplied externally, using a suitable pin, which may be a dedicated reference voltage input pin, or may be a programmable pin which can be programmably selected to function as a reference voltage input pin, or as another kind of pin, such as an I/O pin.
Because the programmable logic device is programmable, and may be used in a configuration in which a reference voltage is not needed, it is desirable to make at least some of the I/O pins programmably configurable either as reference pins or as standard I/O pins having a standard I/O driver or buffer. If a pin is configured as a standard I/O pin, it should be electronically isolated from the reference voltage bus of the programmable logic device. However care must be taken so that a noisy signal on that pin, which may fluctuate to an unexpected voltage, does not overcome that isolation and propagate to the reference voltage bus, where it may cause improper operation or even damage to circuit elements.
SUMMARY OF THE INVENTION
It is an object of this invention to attempt to provide an I/O circuit for a programmable logic device, which circuit is programmably configurable either as a standard I/O driver circuit or as a reference voltage input circuit that in the standard I/O mode protects the reference bus of the programmable logic device in the event that the I/O signal strays to an unexpected voltage value.
In accordance with the present invention, a programmable I/O circuit is provided for use in a programmable logic device that programmably accommodates a plurality of logic signalling standards, at least one of those logic signalling standards requiring a reference voltage. The programmable I/O circuit has an I/O terminal, an I/O buffer coupled to the I/O terminal for buffering I/O signals between the I/O terminal and the programmable logic device. A programmable reference voltage clamp circuit has (a) a first programmable condition in which a reference voltage is passed from the I/O terminal to the programmable logic device, with the I/O buffer being disconnected when the programmable reference voltage clamp is in that first programmable condition, and (b) a second programmable condition in which voltage on the I/O terminal is prevented from being passed through the programmable reference voltage clamp circuit, with the I/O buffer being connected in an operable condition when the programmable reference voltage clamp circuit is in that second programmable condition. The programmable reference voltage clamp circuit has a selection input for controlling when the programmable reference voltage clamp circuit is in the first programmable condition and when it is in the second programmable condition.
In a programmable logic device, or other integrated circuit, which supports a variety of logic signalling standards, some of which may require voltage references, a programmable I/O circuit can be configured as a standard I/O circuit or as a reference voltage input circuit. Such a programmable I/O circuit preferably has a standard I/O buffer which is connected to the programmable logic or other functional portion of the programmable logic or other device, as well as a circuit that can pass a reference voltage to the appropriate location on the programmable logic or other device.
By setting a programming bit or bits to a first condition, one connects the I/O buffer to the I/O pin of the circuit and disconnects the I/O pin from the reference voltage path. In that condition, the programmable I/O circuit functions as a standard I/O circuit. By setting the same programming bit or bits to a second condition, one disconnects the I/O buffer from the programmable logic or other device, while enabling the conduction from the I/O pin of a reference voltage to the appropriate location, such as a reference voltage bus, on the programmable logic or other device. Preferably, the I/O buffer is tristatable, and is disconnected by being placed in a tristated condition.
When the programmable I/O circuit is used as a standard I/O circuit, and the I/O pin is isolated from the reference voltage bus, that isolation preferably is accomplished using a reference voltage pass transistor, which preferably is a field effect transistor. As the voltage of the signal at the I/O pin fluctuates, the gate-to-source voltage across the reference voltage pass transistor may, on a transient basis, assume a state in which the transistor conducts, allowing the signal voltage onto the reference voltage bus. Thus, if the reference voltage pass transistor is an NMOS field effect transistor, the pin voltage could, on a transient basis, become sufficiently negative that the transistor conducts, even though the gate voltage is zero. Conduction by the reference voltage pass transistor could affect the reference if it is in use (a different pin would have to be configured as a reference voltage pin in that case), could damage components connected to the reference voltage bus, or could disturb the states of other pins that use the reference bus to determine their respective states.
Therefore, in accordance with the present invention, the programmable I/O circuit is provided with a reference voltage clamp circuit that pulls the reference voltage pass transistor as strongly as possible into the nonconducting state when it has been programmed to assume that state—i.e., when the programmable I/O circuit is being used as other than a reference voltage input. As described below, this clamp circuit preferably is implemented using NMOS field effect transistors. However, as the reference voltage to be passed approaches the supply voltage, the NMOS transistors will not be able to pass the reference voltage, because the gate-to-source voltage will approach zero, and will therefore be below the conduction threshold (generally 0.7 volts or less) of the transistor. Therefore, in a second preferred embodiment designed to allow a
Huang Joseph
Kim Im Whan
Nguyen Khai
Sung Chiakang
Wang Bonnie I.
Altera Corporation
Chang Daniel D.
Fish & Neave
Ingerman Jeffrey H.
Tokar Michael
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