Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-06-26
2001-09-18
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C365S230030
Reexamination Certificate
active
06292017
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits. More particularly, the present invention relates to programmable logic devices providing improved memory storage.
2. Description of the Related Art
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control, to customize the logic functions the circuit will perform. The logic functions previously performed by small, medium, and large scale integration integrated circuits can instead be performed by programmable logic devices. When a typical programmable logic device is supplied by an integrated circuit manufacturer, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform the specific function or functions required by the user's application. The PLD can then function in a larger system designed by the user just as though dedicated logic chips were employed. For the purpose of this description, it is to be understood that a programmable logic device refers to once programmable as well as reprogrammable devices.
Programmable logic encompasses all digital logic circuits that are configured by the end user, including PLDs, field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). These different programmable logic devices can have substantially different architectures. Once common architecture for PLDs or CPLDs is known as an embedded array programmable logic design.
The general architecture of an embedded array programmable logic design will be generally familiar to those knowledgeable of the FLEX10 logic family of devices manufactured by the Altera Corporation of San Jose, Calif. Such an architecture, for example, is described in U.S. Pat. No. 5,550,782 and
Altera
Data Book 1998, both of which are incorporated herein by reference.
Referring initially to
FIG. 1
, a conventional CPLD
100
with an embedded array programmable logic design will be described. Although only a few logic array blocks or memory blocks are illustrated, it should be appreciated that any number may be provided in order to meet the needs of a particular system.
The CPLD
100
includes a plurality of logic array blocks (LAB)
110
and a plurality of embedded array blocks (EAB)
112
. Each EAB
112
includes a memory array
111
. Each LAB
110
includes a plurality of logic elements LE
113
which are each capable of performing simple logic functions.
As shown in
FIG. 1
, the plurality of LABs
110
and the plurality of EABs
112
are programmably interconnected by way of a plurality global horizontal conductors
114
and a plurality of global vertical conductors
116
to form a logic and memory array. The global horizontal conductors
114
couple to the horizontal ports
108
, and the global vertical conductors
116
couple to the vertical ports
106
.
The EAB is a flexible block of random access memory (RAM) with registers on the input and output ports. As is known in the art, a RAM is an array of individual memory cells, of which each cell includes a plurality of transistors configured to store digital data in the form of a single bit. Typically, the individual memory cells are arranged to form data words of varying length depending upon the particular application. In practice, data words may be of any length, however, data word lengths of 1, 8, 16, or 32 bits are common but any word length desired by the user is possible. As structured, the RAM device has the ability to access, or read, each stored data bit or data independently of any other stored data bit or word by selectively enabling desired rows and columns.
By way of example, the existing FLEX10 family of logic devices include memory cells suitably disposed to store up to 2048 bits (otherwise referred to as 2K bits) of data. For example, in the case of the CPLD
100
, the 2048 memory cells included in each of the memory arrays
111
-
1
and
111
-
2
can be arranged such that the EAB
112
-
1
and the EAB
112
-
2
, respectively, can operate as a single port RAM device having the following dimensions as detailed in Table 1:
TABLE 1
Number of Words (Depth)
Length of Each Word in Bits (Width)
2048
1
1024
2
512
4
256
8
It should be noted that the memory array included in the RAM can be conceptualized as a array having a dimension of “depth” associated with the number of data words having a “width” (or length). As shown in Table 1, the dimensions of the memory array
111
included in the EAB
112
can range from a depth of 2048 words where each word has a width of 1 bit to a depth of 256 words where each word has a width of 8 bits.
Many applications related to high speed data transmission, for example, typically require data words having widths of 16, 32, 64 bits or greater (i.e., the RAM needs to be relatively “wide”). Since these applications typically use the memory cells in the memory array of the RAM devices for only a relatively short period of time (such as, for example, a FIFO-type application), the total amount of memory required is not large (i.e. the RAM can be “shallow” in that the number of data words, or depth, is not large). However, conventional CPLDs having conventional embedded array blocks, such as the CPLD
100
with the EAB
112
-
1
and EAB
112
-
2
, can only store data words of these widths by cascading EABs thereby forming a memory array having appropriate dimensions. By way of example, in order for the conventional CPLD
100
to store data words having widths greater than 8 bits, EAB
112
-
1
and EAB
112
-
2
must be cascaded using a data path created by programmably connecting the horizontal conductors
114
-
1
and
114
-
2
and the vertical conductor
116
-
1
, for example. The data path created by connecting the EAB
112
-
1
and the EAB
112
-
2
is circuitous and results in slow signal propagation speeds which can result in non-functionality. The data path can also require use of a large amount of valuable programming resources which limits the ability of the CPLD
100
to fit applications requiring wide data words. Use of a large amount of programming resources to cascade EABs can also limit the ability of the CPLD to fit ancillary logic functions.
It is therefore desirable to have a programmable logic device that has a memory array that can be efficiently configured in a wide shallow architecture.
SUMMARY OF THE INVENTION
The invention relates to a complex programmable logic device capable of efficiently storing data words of varying length. The programmable logic device is capable of efficiently storing the variable length data words by directly connecting memory blocks using dedicated connectors.
Typically, the complex programmable logic device (CPLD) has various functional blocks and memory blocks included therein. The memory blocks include configurable architecture memory blocks well suited for accommodating data having data words of varying length. The CPLD can be a part of a system such as for example, a reconfigurable computer as well as an ATM switch, or the CPLD can be used as a stand alone chip. Any pair of the configurable memory array blocks of the CPLD can be suitably coupled to a control circuit which controls the connecting of the configurable memory array blocks by the dedicated connectors. Having such a memory array helps to preserve valuable programming resources within the CPLD that would otherwise be required to form the data path required to link various conventional memory arrays. By taking advantage of the reprogrammable nature of the CPLD, the invention is capable of providing a configurable memory array capable of configuring its architecture over a wide range as needed. This capability to reconfigure the memory array substantially increases the number of high speed data retrieval and communication applications to which the CPLD can be used.
One embodiment of the invention pertains to an integrated circuit havi
Altera Corporation
Beyer Weaver & Thomas LLP
Chang Daniel D.
Tokar Michael
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