Programmable logic device incorporating and input/output overflo

Details Programmable logic device incorporating and input/output overflo Programmable logic device incorporating and input/output overflo

1998-07-23

2000-07-25

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, H03K 19177

Patent

active

060940646

ABSTRACT:
A programmable logic device architecture incorporating a peripheral overflow bus is disclosed. In a preferred embodiment, the programmable logic device has a core region that includes at least a plurality of logic cells interconnected by way of associated programmable logic cell conductors. The interconnected logic cells form an array suitable for use in implementing desired logic functions. The programmable logic device also has a peripheral region. The peripheral region includes at least a plurality of bi-directional ports of which selected ones may be coupled to external circuitry. The peripheral region also includes a bi-directional peripheral I/O overflow bus suitably arranged to pass a plurality of control signals and a plurality of data signals between the core region and the plurality of bi-directional ports.

REFERENCES:
patent: 5546018 (1996-08-01), New et al.
patent: 5670897 (1997-09-01), Kean
patent: 5773993 (1998-06-01), Trimberger
Bursky, Dave, "Combination RAM/PLD Opens New Application Options", Electronic Design, pp. 138-140, May 23, 1991.
Intel Corporation "10 ns Flexlogic FPGA with SCRAM Option", Intel.RTM.,iFX780, pp. 2-24 -2-46, Nov. 1993.
NGAI, Tony Kai-Kit, "An SRAM-Programmable Field-Reconfigurable Memory", Department of Electrical Engineering, University of Toronto, Thesis for Master of Applied Science, 1994.

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