Programmable logic device incorporating a memory efficient inter

Details Programmable logic device incorporating a memory efficient inter Programmable logic device incorporating a memory efficient inter

1998-01-30

2000-05-02

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 326 41, 326 44, 326 38, H03K 19177, H03K 19173, H03K 19094

Patent

active

06057707&

ABSTRACT:
The invention relates to an integrated circuit that incorporates a memory efficient interconnection device. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). By using the memory efficient interconnection device, the invention is able to reduce the quantity of memory resources required to program the interconnection device while at the same time not substantially sacrificing the probability of fitting logic functions in the CPLD. The reduction in memory resources that the CPLD must provide leads to increased availability of precious die area for other components of the CPLD.

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patent: 5880597 (1999-03-01), Lee
Bursky, Dave, "Combination RAM/PLD Opens New Application Options", Electronic Design, pp. 138-140, May 23, 1991.
Intel Corporation "10 ns FLEXlogic FPGA with SRAM Option", INTEL.RTM., iFX780, pp. 2-24-2-46, Nov. 1993.
NGAI, Tony Kai-Kit, "An SRAM-Programmable Field-Reconfigurable Memory",Department of Electrical Engineering, University of Toronto, Thesis for Master of Applied Science, 1994.

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