Programmable logic device incorporating a memory efficient...

Details Programmable logic device incorporating a memory efficient... Programmable logic device incorporating a memory efficient...

2000-03-15

2001-07-24

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

06265895

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to programmable logic devices. More specifically, the present invention relates to interconnecting logic and memory elements included within programmable logic devices.
2. Description of the Related Art
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control, to program particular logic functions the circuit will perform. Logic functions performed by small, medium, and large-scale integration integrated circuits can instead be performed by programmable logic devices. When an integrated circuit manufacturer supplies a typical programmable logic device, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform particular functions required by the user's application. The PLD then can function in a larger system designed by the user just as though dedicated logic chips were employed. For the purpose of this description, it is to be understood that a programmable logic device refers to once programmable devices as well as reprogrammable devices.
Programmable logic encompasses all digital logic circuits that are configured by the end user, including PLDs, field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). The general architecture of the embedded array programmable logic design will be generally familiar to those knowledgeable of the FLEX10K™ logic family of devices manufactured by the Altera Corporation of San Jose, Calif. Such an architecture, for example, is described in U.S. Pat. No. 5,550,782 and Altera Data Book 1996, both of which are incorporated herein by reference. Referring initially to
FIGS. 1 and 2
, a CPLD
100
with an embedded array programmable logic design will be described. Although only a few logic array blocks or memory blocks are illustrated, it should be appreciated that any number may be provided in order to meet the needs of a particular system.
The CPLD
100
includes a core region
120
and a peripheral region
121
. The peripheral region
121
includes a plurality of vertical bidirectional ports
160
and a plurality of horizontal ports
162
. The core region
120
includes a plurality of logic array blocks (LAB)
102
and a plurality of embedded array blocks (EAB)
104
. Each EAB
104
includes an array of memory elements. Each LAB
102
includes a plurality of logic elements (LE) each of which is capable of performing simple logic functions. An internal logic interconnect included within each LAB serves to interconnect each of the logic elements included therein.
As shown in
FIG. 1
, the plurality of LABs
102
and the plurality of EABs
104
are programmably interconnected by way of a plurality global horizontal conductors
190
and a plurality of global vertical conductors
192
to form a logic and memory array. The global horizontal conductors
190
couple to the horizontal ports
162
, and the global vertical conductors
192
, couple to the vertical ports
160
.
For example, the horizontal bidirectional port
162
-
1
can be selectively coupled to a global horizontal conductor
190
-
1
(and all row channels included therein) so that core region
120
may communicate with external circuitry connected to the horizontal bidirectional port
162
-
1
. Such external circuitry may, for example, include processing systems such as Pentium™ based PCs or Sun SPARCstations™. Such processing systems are capable of executing automatic place and route software such as, for example, MAX+PLUS II™ developed by the Altera Corporation of San Jose, Calif. In a procedure known in the art as fitting a logic function, such automatic place and route software is used to logically couple previously programmed logic and memory units included within core region
120
. In this manner, CPLD
100
is programmed to perform the logic function as desired.
Additional details of the CPLD
100
are explained with reference to a representative portion
110
of the core region
120
illustrated in FIG.
1
. The representative portion
110
has the global horizontal conductor
190
-
1
coupled to EAB
104
-
1
by way of a plurality of local vertical conductors
134
and a plurality of local horizontal conductors
136
. The local vertical conductors
134
are programmably coupled to the global horizontal conductor
190
-
1
by way of a programmable interconnect array (PIA)
132
. The local vertical conductors
134
are also programmably coupled to the local horizontal conductors
136
by way of a programmable interconnect region
133
. The local horizontal conductors
136
in turn couple to the EAB
104
-
1
.
In order to fit a desired logic function, various logic elements and/or memory blocks are individually configured to perform a small but crucial part of the overall logic and/or memory function. Any automatic place and route software must then logically connect all the programmed logic elements and/or memory elements such that CPLD
100
may execute the desired logic function and or memory-logic function.
FIG. 2
illustrates a detailed view of the representative portion
110
of core region
120
. The programmable interconnect region
133
includes a group of programmable connectors
150
associated with the local horizontal conductors
136
. The group of programmable connectors
150
can selectively connect the local horizontal conductors
136
to the local vertical conductors
134
. The programmable interconnect array
132
includes a group of programmable connectors
142
. The group of programmable connectors
142
can selectively connect the local vertical conductors
134
to a plurality of row channels
194
included in the global horizontal conductor
190
-
1
.
In order to fit a logic and/or a logic-memory function any place and route software can program selected ones of the programmable connectors
142
and programmable connectors
150
to connect the EAB
104
-
1
to certain of the row channels
194
using, for example, the local horizontal conductors
136
and the local vertical conductors
134
. The local horizontal conductors
136
connect to EAB I/O lines
105
of the EAB
104
-
1
. The EAB I/O line
105
-
1
is connected to a selected local horizontal row conductor
136
-
1
having an associated group of programmable connectors
140
-
1
. The place and route software can then direct a programmable connector
150
-
1
included in the group of connectors
140
-
1
to connect the local horizontal conductor
136
-
1
to the local vertical conductor
134
-
1
. The local vertical conductor
134
-
1
has an associated group of programmable connectors
144
-
1
. The place and route software can further direct another selected programmable connector
142
-
1
included in the group of programmable connectors
144
-
1
to connect the local vertical conductor
134
-
1
to the row channel
194
-
1
. In this manner, the EAB
104
-
1
can communicate with row channel
194
-
1
included in the global horizontal conductor
190
-
1
as well as with any circuitry connected thereto.
Each of the programmable connectors
150
and each of the programmable connectors
142
are controlled by individual switching devices
131
. The individual switching devices
131
are switched between a connect state or a no-connect state by memory cells
135
included in the CPLD
100
. As shown in
FIG. 2A
, for example, the representative programmable connector
150
-
1
is shown connected to an associated memory cell
135
by way of a memory cell node
131
. The memory cell
135
must be capable of setting the programmable connector
150
-
1
to a connect state or a no-connect state depending on whether the associated local horizontal conductor
136
-
1
is programmably connected to the local vertical conductor
134
-
1
.
The large quantity of memory cells
135
necessary to assure a high probability of fitting a complex function consumes large amou

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