Static information storage and retrieval – Systems using particular element – Semiconductive
Patent
1997-12-30
1999-09-28
Fears, Terrell W.
Static information storage and retrieval
Systems using particular element
Semiconductive
365 51, 365 63, G11C 1300
Patent
active
059598816
ABSTRACT:
A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.
REFERENCES:
patent: 3775756 (1973-11-01), Balser
patent: 4189782 (1980-02-01), Dingwezc
patent: 4237545 (1980-12-01), Deglin et al.
patent: 4288658 (1981-09-01), Bieber et al.
patent: 4434461 (1984-02-01), Puhl
patent: 4594661 (1986-06-01), Moore et al.
patent: 4661901 (1987-04-01), Veneski
patent: 4750155 (1988-06-01), Hsieh
patent: 4821233 (1989-04-01), Hsieh
patent: 5019996 (1991-05-01), Lee
patent: 5042004 (1991-08-01), Agrawal et al.
patent: 5053995 (1991-10-01), Kajimura
patent: 5081375 (1992-01-01), Pickett et al.
patent: 5144242 (1992-09-01), Zeilenga et al.
patent: 5155389 (1992-10-01), Furtek
patent: 5155390 (1992-10-01), Hickman et al.
patent: 5185706 (1993-02-01), Agrawal et al.
patent: 5224056 (1993-06-01), Chene et al.
patent: 5245227 (1993-09-01), Furtek et al.
patent: 5349248 (1994-09-01), Parlour et al.
patent: 5377331 (1994-12-01), Drerup et al.
patent: 5426378 (1995-06-01), Ong
patent: 5426738 (1995-06-01), Hsieh et al.
patent: 5426744 (1995-06-01), Sawase et al.
patent: 5432388 (1995-07-01), Crafts et al.
patent: 5469368 (1995-11-01), Agrawal et al.
patent: 5469577 (1995-11-01), Eng et al.
patent: 5513124 (1996-04-01), Trimberger et al.
patent: 5521835 (1996-05-01), Trimberger
patent: 5526276 (1996-06-01), Cox et al.
patent: 5530654 (1996-06-01), Takahashi
patent: 5553002 (1996-09-01), Dangelo et al.
patent: 5583450 (1996-12-01), Trimberger et al.
patent: 5600263 (1997-02-01), Trimberger et al.
patent: 5629637 (1997-05-01), Trimberger et al.
patent: 5646545 (1997-07-01), Trimberger et al.
patent: 5701441 (1997-12-01), Trimberger et al.
"The Programmable Logic Data Book" copyright 1994, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
"Principles of CMOS VLSI Design, A Systems Perspective", N. Weste & K. Eshraghian, Addison-Wesley Publishing Company, 1988, pp. 160-164.
Paper presented at IEEE Workshop on FPGA's for Custom Computing Machines, FCCM '93, Apr. 1993 entitled "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", Jonathan Babb, et al. Jan. 26, 1993, pp. 1-15.
Narasimha B. Bhat, Kamal Chaudhary, and Ernest S. Kuh, "Performance-Oriented Fully Routable Dynamic Architecture for a Field Programmable Logic Device", Electronic Research Laboratory, College of Engineering, University of California, Berkeley, Jun. 1, 1993.
Andre DeHon, "DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century", NE43-791, 545 Technology Square, Cambridge, MA 02139, 10 pages, Jan. 6, 1994.
Chi-Yuan Chin, et al., "A Dynamically Reconfigurable Interconnection Chip" Session XX: Special Purpose Accelerators; IEEE International Solid State Circuits Conference, pp. 276-277, 425, Feb. 27, 1987.
David M. Lewis, "Hierarchical Compiled Event-Driven Logic Simulation", Department of Electrical Engineering, University of Toronto, IEEE, 1989, pp. 498-501.
Trimberger, Stephen M., "A Reprogrammable Gate Array and Applications," Proceedings of the IEEE, vol. 81, No. 7, Jul. 1993, pp. 1030-1041.
Trimberger, Stephen M. and Chene, Mon-Ren, "Placement-Based Partitiioning for Lookup-Table-Based FPGAs," IEEE, Computer Design--ICCD '92, 1992 International Conference, pp. 91-94.
Laung-Terng Wang, et al. "SSIM: A Software Levelized Compiled-Code Simulator", 24th ACM/IEEE Design Automation Conference, 1987, Paper 2.1, pp. 2-8.
Randal E. Bryant, et al. "COSMOS: A Compiled Simulator for MOS Circuits", 24th ACM/IEEE Design Automation Conference, 1987, Paper 2.2, pp. 9-16.
Peter M. Maurer, "Scheduling Blocks of Hierarchical Compiled Simulation of Combinational Circuits", IEEE Transactions on Computer-Aided Design, vol. 10, No. 2, Feb. 1991, pp. 184-192.
Carberry Richard A.
Johnson Robert Anders
Trimberger Stephen M.
Wong Jennifer
Behiel Arthur Joseph
Fears Terrell W.
Harms Jeanette S.
Xilinx , Inc.
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